Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1835

MOVLPS: Move Low Packed Single-FP
Opcode
0F,12,/r
0F,13,/r
Operation: if (destination == xmm) {
// load instruction
xmm[63-0]
xmm[95-64]
xmm[127-96] = xmm[127-96];
}
else {
// store instruction
m64 = xmm[63-0];
}
The linear address corresponds to the address of the least-significant byte of the
Description:
referenced memory data. When the load form of this operation is used, m64 is loaded
into the lower 64-bits of the 128-bit register xmm and the upper 64-bits are left
unchanged.
None
FP Exceptions:
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF (fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #AC for unaligned memory
reference. To enable #AC exceptions, three conditions must be true(CR0.AM is set;
EFLAGS.AC is set; current CPL is 3); #UD if CRCR4.OSFXSR(bit 9) = 0; #UD if
CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set.; #UD if
CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF (fault-code) for a page fault; #AC for
unaligned memory reference if the current privilege level is 3.
Volume 4: IA-32 SSE Instruction Reference
Instruction
MOVLPS xmm, m64
MOVLPS m64, xmm
= m64;
= xmm[95-64];
Description
Move 64 bits representing two SP operands from Mem to
lower two fields of XMM register.
Move 64 bits representing two SP operands from lower two
fields of XMM register to Mem.
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