Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1060

ldfp — Floating-point Load Pair
( ) ldfps.
Format: qp fldtype
( ) ldfps.
qp fldtype
( ) ldfpd.
qp fldtype
( ) ldfpd.
qp fldtype
( ) ldfp8.
qp fldtype
( ) ldfp8.
qp fldtype
Eight (single_form) or sixteen (double_form/integer_form) bytes are read from
Description:
memory starting at the address specified by the value in GR
treated as a contiguous pair of floating-point numbers for the single_form/double_form
and as integer/Parallel FP data for the integer_form. Each number is converted into the
floating-point register format. The value at the lowest address is placed in FR
value at the highest address is placed in FR
Formats" on page 1:85
fldtype completer specifies special load operations, which are described in
page 3:157.
For more details on speculative, advanced and check loads see
Speculation" on page 1:60
For the non-speculative load types, if NaT bit associated with GR
Consumption fault is taken. For speculative and speculative advanced loads, no fault is
raised, and the exception is deferred.
In the base_update_form, the value in GR
(equal to double the data size) and the result is placed back in GR
update is done after the load, and does not affect the load address.
The value of the ldhint modifier specifies the locality of the memory access. The
mnemonic values of ldhint are given in
implied in the base update form. The address specified by the value in GR
base update acts as a hint to prefetch the indicated cache line. This prefetch uses the
locality hints specified by ldhint. Prefetch and locality hints do not affect program
functionality and may be ignored by the implementation. See
Hierarchy Control and Consistency" on page 1:69
In the no_base_update form, the value in GR r
implied.
The PSR.mfl and PSR.mfh bits are updated to reflect the modification of FR f
There is a restriction on the choice of target registers. Register specifiers f
specify one odd-numbered physical FR and one even-numbered physical FR. Specifying
two odd or two even registers will cause an Illegal Operation fault to be raised. The
restriction is on physical register numbers after register rotation. This means that if f
and f both specify static registers or both specify rotating registers, then f
2
must be odd/even or even/odd. If f
the restriction depends on CFM.rrb.fr. If CFM.rrb.fr is even, the restriction is the same;
f and f must be odd/even or even/odd. If CFM.rrb.fr is odd, then f
1 2
even/even or odd/odd. Specifying one static and one rotating register should only be
done when CFM.rrb.fr will have a predictable value (such as 0).
Volume 3: Instruction Reference
. , = [ ]
ldhint f f r
1 2 3
. , = [ ], 8
ldhint f f r
1 2 3
. , = [ ]
ldhint f f r
1 2 3
. , = [ ], 16
ldhint f f r
1 2 3
. , = [ ]
ldhint f f r
1 2 3
. , = [ ], 16
ldhint f f r
1 2 3
for details on conversion to floating-point register format. The
and Section 4.4.5, "Data Speculation" on page
and f
1
single_form, no_base_update_form
single_form, base_update_form
double_form, no_base_update_form
double_form, base_update_form
integer_form, no_base_update_form
integer_form, base_update_form
r
3
. See Section 5.1, "Data Types and
f
2
is added to an implied immediate value
r
3
Table 2-34 on page 3:152. A prefetch hint is
Section 4.4.6, "Memory
for details.
is not modified and no prefetch hint is
3
specify one static and one rotating register,
2
ldfp
M11
M12
M11
M12
M11
M12
. The value read is
, and the
f
1
Table 2-36 on
Section 4.4.4, "Control
1:63.
is 1, a Register NaT
r
3
. This base register
r
3
after the
r
3
and FR f
1 2
and f must
1 2
1
and f
1 2
and f must be
1 2
3:161
.