Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1724

PANDN—Logical AND NOT (continued)
Protected Mode Exceptions
#GP(0)
#SS(0)
#UD
#NM
#MF
#PF(fault-code)
#AC(0)
Real-Address Mode Exceptions
#GP
#UD
#NM
#MF
Virtual-8086 Mode Exceptions
#GP
#UD
#NM
#MF
#PF(fault-code)
#AC(0)
4:422
If a memory operand effective address is outside the CS, DS, ES, FS
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If EM in CR0 is set.
If TS in CR0 is set.
If there is a pending FPU exception.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If any part of the operand lies outside of the effective address space
from 0 to FFFFH.
If EM in CR0 is set.
If TS in CR0 is set.
If there is a pending FPU exception.
If any part of the operand lies outside of the effective address space
from 0 to FFFFH.
If EM in CR0 is set.
If TS in CR0 is set.
If there is a pending FPU exception.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made.
Volume 4: IA-32 Intel
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MMX™ Technology Instruction Reference