Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1052

Table 2-34. Load Hints (Continued)
ldhint Completer
In the no_base_update form, the value in GR r
implied.
For the base update forms, specifying the same register address in r
an Illegal Operation fault.
Hardware support for ld16 instructions that reference a page that is neither a
cacheable page with write-back policy nor a NaTPage is optional. On processor models
that do not support such ld16 accesses, an Unsupported Data Reference fault is raised
when an unsupported reference is attempted.
For the sixteen_byte_form, Illegal Operation fault is raised on processor models that do
not support the instruction. CPUID register 4 indicates the presence of the feature on
the processor model. See
page 1:34
Volume 3: Instruction Reference
nt1 No temporal locality, level 1
nta No temporal locality, all levels
Section 3.1.11, "Processor Identification Registers" on
for details.
Interpretation
is not modified and no prefetch hint is
3
and r
1
ld
will cause
3
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