Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1878

MASKMOVQ: Byte Mask Write
Opcode
0F,F7,/r
Operation: if (mm2[7])
if (mm2[15])
if (mm2[23])
if (mm2[31])
if (mm2[39])
if (mm2[47])
if (mm2[55])
if (mm2[63])
Data is stored from the mm1 register to the location specified by the di/edi register
Description:
(using DS segment). The size of the store address depends on the address-size
attribute. The most significant bit in each byte of the mask register mm2 is used to
selectively write the data (0 = no write, 1 = write), on a per-byte basis. Behavior with a
mask of all zeroes is as follows:
• No data will be written to memory. However, transition from FP to MMX technology
state (if necessary) will occur, irrespective of the value of the mask.
• For memory references, a zero byte mask does not prevent addressing faults (i.e.
#GP, #SS) from being signalled.
• Signalling of page faults (#PF) is implementation specific.
• #UD, #NM, #MF, and #AC faults are signalled irrespective of the value of the mask.
• Signalling of breakpoints (code or data) is not guaranteed; different processor
implementations may signal or not signal these breakpoints.
• If the destination memory region is mapped as UC or WP, enforcement of
associated semantics for these memory types is not guaranteed (i.e. is reserved)
and is implementation specific. Dependency on the behavior of a specific
implementation in this case is not recommended, and may lead to future
incompatibility.
The Mod field of the ModR/M byte must be 11, or an Invalid Opcode Exception will
result.
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF (fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a pending FPU
exception; #AC for unaligned memory reference. To enable #AC exceptions, three
conditions must be true(CR0.AM is set; EFLAGS.AC is set; current CPL is 3).
4:576
Instruction
MASKMOVQ mm1, mm2
m64[edi] = mm1[7-0];
m64[edi+1] = mm1[15-8];
m64[edi+2] = mm1[23-16];
m64[edi+3] = mm1[31-24];
m64[edi+4] = mm1[39-32];
m64[edi+5] = mm1[47-40];
m64[edi+6] = mm1[55-48];
m64[edi+7] = mm1[63-56];
Description
Move 64-bits representing integer data from MM1 register to
memory location specified by the edi register, using the byte
mask in MM2 register.
Volume 4: IA-32 SSE Instruction Reference