Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1050
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ld — Load
(
) ld
.
Format:
qp
sz
ldtype
(
) ld
.
qp
sz
ldtype
(
) ld
.
qp
sz
ldtype
(
) ld16.
qp
ldhint r
(
) ld16.acq.
qp
(
) ld8.fill.
qp
(
) ld8.fill.
qp
(
) ld8.fill.
qp
A value consisting of sz bytes is read from memory starting at the address specified by
Description:
the value in GR
the sz completer are given in
except as described below for speculative loads. The ldtype completer specifies special
load operations, which are described in
For the sixteen_byte_form, two 8-byte values are loaded as a single, 16-byte memory
read. The value at the lowest address is placed in GR
address is placed in the Compare and Store Data application register (AR[CSD]). The
only load types supported for this sixteen_byte_form are
For the fill_form, an 8-byte value is loaded, and a bit in the UNAT application register is
copied into the target register NaT bit. This instruction is used for reloading a spilled
register/NaT pair. See
In the base update forms, the value in GR
value (
imm
register update is done after the load, and does not affect the load address. In the
reg_base_update_form, if the NaT bit corresponding to GR
corresponding to GR
supported for the ld16 instruction.
Table 2-32.
Table 2-33.
ldtype
Completer
none
s
a
Volume 3: Instruction Reference
.
= [
]
ldhint r
r
1
3
.
= [
],
ldhint r
r
r
1
3
2
.
= [
],
ldhint r
r
imm
1
3
9
, ar.csd = [
]
r
1
3
, ar.csd = [
]
ldhint r
r
1
3
= [
]
ldhint r
r
1
3
= [
],
ldhint r
r
r
1
3
2
= [
],
ldhint r
r
imm
1
3
9
. The value is then zero extended and placed in GR
r
3
Table
Section 4.4.4, "Control Speculation" on page 1:60
) or a value from GR
r
9
2
is set and no fault is raised. Base register update is not
r
3
sz Completers
sz Completer
1
2
4
8
Load Types
Interpretation
Normal load
Speculative load
Certain exceptions may be deferred rather than generating a fault.
Deferral causes the target register's NaT bit to be set. The NaT bit is
later used to detect deferral.
Advanced load
An entry is added to the ALAT. This allows later instructions to check for
colliding stores. If the referenced data page has a non-speculative
attribute, the target register and NaT bit is cleared, and the processor
ensures that no ALAT entry exists for the target register. The absence of
an ALAT entry is later used to detect deferral or collision.
sixteen_byte_form, no_base_update_form
sixteen_byte_form, acquire_form,
fill_form, no_base_update_form
fill_form, reg_base_update_form
fill_form, imm_base_update_form
2-32. The NaT bit corresponding to GR
Table
2-33.
, and the value at the highest
r
1
is added to either a signed immediate
r
3
, and the result is placed back in GR
Bytes Accessed
Special Load Operation
no_base_update_form
reg_base_update_form
imm_base_update_form
no_base_update_form
. The values of
r
1
is cleared,
r
1
and
.
none
acq
for details.
. This base
r
3
is set, then the NaT bit
r
2
1 byte
2 bytes
4 bytes
8 bytes
ld
M2
M2
M3
M2
M2
M2
M2
M3
3:151
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