Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1183

Table 3-1. Pseudo-code Functions (Continued)
Function
impl_check_mov_itir()
impl_check_mov_psr_l(gr)
impl_check_tlb_itir()
impl_gitc_enable()
impl_ia32_ar_reserved_ignored(ar3)
impl_iib()
impl_itir_cwi_mask()
impl_ito()
impl_probe_intercept()
impl_ruc()
impl_uia_fault_supported()
implemented_vm()
instruction_implemented(inst)
instruction_serialize()
instruction_synchronize()
is_finite(freg)
is_ignored_reg(regnum)
is_inf(freg)
is_interruption_cr(regnum)
is_kernel_reg(ar_addr)
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Intel Itanium Architecture Software Developer's Manual Rev. 2.3
Implementation-specific function that returns TRUE if ITIR is checked for reserved
fields and encodings on a mov to ITIR instruction.
Implementation-specific function to check bits {63:32} of gr corresponding to
reserved fields of the PSR for Reserved Register/Field fault.
Implementation-specific function that returns TRUE if all fields of ITIR are checked for
reserved encodings on a TLB insert instruction regardless of whether the translation
is present.
Implementation-specific function that indicates whether guest MOV-from-AR.ITC
optimization is enabled.
Implementation-specific function which indicates how the reserved and ignored fields
in the specified IA-32 application register, ar3 , behave. If it returns FALSE, the
reserved and/or ignored bits in the specified application register can be written, and
when read they return the value most-recently written. If it returns TRUE, attempts to
write a non-zero value to a reserved field in the specified application register cause a
Reserved Register/Field fault, and reads return 0; writing to an ignored field in the
specified application register is ignored, and reads return the constant value defined
for that field.
Implementation-specific function which indicates whether Interruption Instruction
Bundle registers (IIB0-1) are implemented.
Implementation-specific function that either returns the value passed to it or the value
passed to it masked with zeros in bit positions {63:32} and/or {1:0}.
Implementation-specific function which indicates whether Interval Timer Offset (ITO)
register is implemented.
Implementation-specific function indicates whether probe interceptions are
supported.
Implementation-specific function which indicates whether Resource Utilization
Counter (RUC) application register is implemented.
Implementation-specific function that either returns TRUE if the processor reports
unimplemented instruction addresses with an Unimplemented Instruction Address
fault, and returns FALSE if the processor reports them with an Unimplemented
Instruction Address trap.
Returns TRUE if the processor implements the PSR.vm bit (regardless of whether
virtual machine features are enabled or disabled).
Implementation-dependent routine which returns TRUE or FALSE, depending on
whether inst is implemented.
Ensures all prior register updates with side-effects are observed before subsequent
instruction and data memory references are performed. Also ensures prior SYNC.i
operations have been observed by the instruction cache.
Synchronizes the instruction and data stream for Flush Cache operations. This
function ensures that when prior Flush Cache operations are observed by the local
data cache they are observed by the local instruction cache, and when prior Flush
Cache operations are observed by another processor's data cache they are observed
within the same processor's instruction cache.
Returns true when floating register contains a finite number.
Boolean function that returns true if regnum is an ignored application register,
otherwise false.
Returns true when floating register contains an infinite number.
Boolean function that returns true if regnum is one of the Interruption Control
registers (see Section 3.3.5, "Interruption Control Registers" on page
false.
Returns a one if ar_addr is the address of a kernel register application register
Operation
Volume 3: Pseudo-Code Functions
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