Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1156

sum — Set User Mask
( ) sum
Format: qp imm
The
Description: imm
24
the user mask. See
PSR.up can only be set if the secure performance monitor bit (PSR.sp) is zero.
Otherwise PSR.up is not modified.
Operation: if (PR[qp]) {
if (is_reserved_field(PSR_TYPE, PSR_UM, imm
reserved_register_field_fault();
if (imm
if (imm
if (imm
if (imm
if (imm
}
Reserved Register/Field fault
Interruptions:
All user mask modifications are observed by the next instruction group.
Serialization:
Volume 3: Instruction Reference
24
operand is ORed with the user mask (PSR{5:0}) and the result is placed in
Section 3.3.2, "Processor Status Register (PSR)" on page
{1}) PSR{1} = 1;)
24
{2} && PSR.sp == 0)
24
PSR{2} = 1;)
{3}) PSR{3} = 1;)
24
{4}) PSR{4} = 1;)
24
{5}) PSR{5} = 1;)
24
))
24
// be
//non-secure perf monitor
// up
// ac
// mfl
// mfh
sum
M44
2:23.
3:257