Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1320

high-order within registers and within memory bytes. If the base operand is a
register, the offset can be in the range 0..31. This offset addresses a bit within the
indicated register. An example, the function Bit[EAX, 21] is illustrated in
Figure 2-2.
If BitBase is a memory address, BitOffset can range from -2 GBits to 2 GBits. The
addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase +
(BitOffset DIV 8)), where DIV is signed division with rounding towards negative infinity,
and MOD returns a positive number. This operation is illustrated in
Figure 2-3.
2.2.3 Flags Affected
The "Flags Affected" section lists the flags in the EFLAGS register that are affected by
the instruction. When a flag is cleared, it is equal to 0; when it is set, it is equal to 1.
The arithmetic and logical instructions usually assign values to the status flags in a
uniform manner (see Appendix A, EFLAGS Cross-Reference, in the Intel Architecture
Software Developer's Manual, Volume 1). Non-conventional assignments are described
in the "Operation" section. The values of flags listed as undefined may be changed by
the instruction in an indeterminate manner. Flags that are not listed are unchanged by
the instruction.
2.2.4 FPU Flags Affected
The floating-point instructions have an "FPU Flags Affected" section that describes how
each instruction can affect the four condition code flags of the FPU status word.
4:18
Bit Offset for BIT[EAX,21]
31 21
Memory Bit Indexing
7 5 0 7
BitBase +1
BitOffset = +13
7 0 7
BitBase
BitOffset = 21
0 7
BitBase BitBase -1
0 7 5
BitBase -1 BitBase -2
BitOffset = -11
Volume 4: Base IA-32 Instruction Reference
Figure 2-2.
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Figure 2-3.
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