Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1791

ANDPS: Bit-wise Logical And for Single-FP
Opcode
0F,54,/r
Operation: xmm1[127-0] &= xmm2/m128[127-0];
The ANDPS instruction returns a bit-wise logical AND between XMM1 and XMM2/Mem.
Description:
General protection exception if not aligned on 16-byte boundary, regardless of
FP Exceptions:
segment.
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if CRCR4.OSFXSR(bit 9) =
0; #UD if CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if
CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
The usage of Repeat Prefixes (F2H, F3H) with ANDPS is reserved. Different processor
Comments:
implementations may handle this prefix differently. Usage of this prefix with ANDPS
risks incompatibility with future processors.
Volume 4: IA-32 SSE Instruction Reference
Instruction
ANDPS xmm1, xmm2/m128
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault
Description
Logical AND of 128 bits from XMM2/Mem to XMM1 register.
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