Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1294

Table 5-5. Instruction Classes (Continued)
Class
rse-readers
rse-writers
st
st-postinc
stf
sxt
sys-mask-writers-partial
unpack
unpredicatable-instructions
user-mask-writers-partial
xchg
zxt
Volume 3: Resource and Dependency Semantics
alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, mov-from-AR-BSP ,
mov-from-AR-BSPSTORE , mov-to-AR-BSPSTORE , mov-from-AR-RNAT ,
mov-to-AR-RNAT , rfi
alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, mov-to-AR-BSPSTORE , rfi
st1, st2, st4, st8, st8.spill, st16
stf [Format in {M10}], st [Format in {M5}]
stfs, stfd, stfe, stf8, stf.spill
sxt1, sxt2, sxt4
rsm, ssm
unpack1, unpack2, unpack4
alloc, br.cloop, br.ctop, br.cexit, br.ia, brp, bsw, clrrrb, cover, epc, flushrs, loadrs, rfi, vmsw
rum, sum
xchg1, xchg2, xchg4, xchg8
zxt1, zxt2, zxt4
Events/Instructions
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