Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 925

br
tmp_taken = PR[qp];
if (tmp_taken) {
}
break;
case 'ia':
tmp_taken = 1;
if (PSR.ic == 0 || PSR.dt == 0 || PSR.mc == 1 || PSR.it == 0)
if (qp != 0)
if (AR[BSPSTORE] != AR[BSP])
if (PSR.di)
PSR.is = 1;
CFM.sof = 0;
CFM.sol = 0;
CFM.sor = 0;
CFM.rrb.gr = 0;
CFM.rrb.fr = 0;
CFM.rrb.pr = 0;
rse_invalidate_non_current_regs();
//compute effective instruction pointer
EIP{31:0} = tmp_IP{31:0} - AR[CSD].Base;
// Note the register stack is disabled during IA-32 instruction
// set execution
break;
case 'cloop':
if (slot != 2)
3:26
// tmp_growth indicates the amount to move logical TOP *up*:
// tmp_growth = sizeof(previous out) - sizeof(current frame)
// a negative amount indicates a shrinking stack
tmp_growth = (AR[PFS].pfm.sof - AR[PFS].pfm.sol) - CFM.sof;
alat_frame_update(-AR[PFS].pfm.sol, 0);
rse_fatal = rse_restore_frame(AR[PFS].pfm.sol,
if (rse_fatal) {
// See Section 6.4, "RSE Operation" on page 2:137
CFM.sof = 0;
CFM.sol = 0;
CFM.sor = 0;
CFM.rrb.gr = 0;
CFM.rrb.fr = 0;
CFM.rrb.pr = 0;
} else // normal branch return
CFM = AR[PFS].pfm;
rse_enable_current_frame_load();
AR[EC] = AR[PFS].pec;
if (PSR.cpl u< AR[PFS].ppl) {
PSR.cpl = AR[PFS].ppl;
lower_priv_transition = 1;
}
undefined_behavior();
illegal_operation_fault();
illegal_operation_fault();
disabled_instruction_set_transition_fault();
tmp_growth, CFM.sof);
// ... and restores privilege
// switch to IA mode
// set IA-32 Instruction Set Mode
//force current stack frame
//to zero
// simple counted loop
Volume 3: Instruction Reference