Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1769

The DIVPS (Divide packed single-precision floating-point) instruction divides four pairs
of packed single-precision floating-point operands.
The DIVSS (Divide scalar single-precision floating-point) instruction divides the least
significant pair of packed single-precision floating-point operands; the upper three
fields are passed through from the source operand.
Packed/Scalar Square Root
The SQRTPS (Square root packed single-precision floating-point) instruction returns the
square root of the packed four single-precision floating-point numbers from the source
to a destination register.
The SQRTSS (Square root scalar single-precision floating-point) instruction returns the
square root of the least significant component of the packed single-precision
floating-point numbers from source to a destination register; the upper three fields are
passed through from the source operand.
Packed Maximum/Minimum
The MAXPS (Maximum packed single-precision floating-point) instruction returns the
maximum of each pair of packed single-precision floating-point numbers into the
destination register.
The MAXSS (Maximum scalar single-precision floating-point) instructions returns the
maximum of the least significant pair of packed single-precision floating-point numbers
into the destination register; the upper three fields are passed through from the source
operand, to the destination register.
The MINPS (Minimum packed single-precision floating-point) instruction returns the
minimum of each pair of packed single-precision floating-point numbers into the
destination register.
The MINSS (Minimum scalar single-precision floating-point) instruction returns the
minimum of the least significant pair of packed single-precision floating-point numbers
into the destination register; the upper three fields are passed through from the source
operand, to the destination register
4.6.1.2 Logical Instructions
The ANDPS (Bit-wise packed logical AND for single-precision floating-point) instruction
returns a bitwise AND between the two operands.
The ANDNPS (Bit-wise packed logical AND NOT for single-precision floating-point)
instruction returns a bitwise AND NOT between the two operands.
The ORPS (Bit-wise packed logical OR for single-precision floating-point) instruction
returns a bitwise OR between the two operands.
The XORPS (Bit-wise packed logical XOR for single-precision floating-point) instruction
returns a bitwise XOR between the two operands.
Volume 4: IA-32 SSE Instruction Reference 4:467