Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1153

Hide thumbs Also See for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3:
Table of Contents

Advertisement

stf
stf — Floating-point Store
(
) stf
.
Format:
qp
fsz
sthint
(
) stf
.
qp
fsz
sthint
(
) stf8.
qp
sthint
(
) stf8.
qp
sthint
(
) stf.spill.
qp
(
) stf.spill.
qp
A value, consisting of fsz bytes, is generated from the value in FR
Description:
memory starting at the address specified by the value in GR
value in FR
the significand of FR
on page
3:157. In the normal_form or the integer_form, if the NaT bit corresponding to
GR
is 1 or if FR
r
3
Section 5.1, "Data Types and Formats" on page 1:85
floating-point register format.
In the spill_form, a 16-byte value from FR
instruction is used for spilling a register. See
page 1:60
In the imm_base_update form, the value in GR
(
) and the result is placed back in GR
imm
9
store, and does not affect the store address.
The ALAT is queried using the physical memory address and the access size, and all
overlapping entries are invalidated.
The value of the sthint completer specifies the locality of the memory access. The values
of the sthint completer are given in
in the base update forms. The address specified by the value in GR
update acts as a hint to prefetch the indicated cache line. This prefetch uses the locality
hints specified by sthint. See
Consistency" on page
Hardware support for stfe (10-byte) instructions that reference a page that is neither a
cacheable page with write-back policy nor a NaTPage is optional. On processor models
that do not support such stfe accesses, an Unsupported Data Reference fault is raised
when an unsupported reference is attempted.
3:254
[
] =
r
f
3
2
[
] =
,
r
f
imm
3
2
9
[
] =
r
f
3
2
[
] =
,
r
f
imm
3
2
9
[
] =
sthint
r
f
3
2
[
] =
,
sthint
r
f
imm
3
2
9
is converted to the memory format and then stored. In the integer_form,
f
2
is stored. The values of the fsz completer are given in
f
2
contains NaTVal, a Register NaT Consumption fault is taken. See
f
2
for details.
Section 4.4.6, "Memory Hierarchy Control and
1:69.
normal_form, no_base_update_form
normal_form, imm_base_update_form
integer_form, no_base_update_form
integer_form, imm_base_update_form
spill_form, no_base_update_form
spill_form, imm_base_update_form
for details on conversion from
is stored without conversion. This
f
2
Section 4.4.4, "Control Speculation" on
is added to a signed immediate value
r
3
. This base register update is done after the
r
3
Table 2-51 on page
3:252. A prefetch hint is implied
and written to
f
2
. In the normal_form, the
r
3
Table 2-35
after the base
r
3
Volume 3: Instruction Reference
M13
M10
M13
M10
M13
M10

Advertisement

Table of Contents
loading

This manual is also suitable for:

Itanium architecture 2.3

Table of Contents