Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1167

tpa
tpa — Translate to Physical Address
( ) tpa
Format: qp r
1
The physical address for the virtual address specified by GR
Description:
GR .
r
1
When PSR.dt is 1, the DTLB and the VHPT are searched for the virtual address specified
by GR and the region register indexed by GR
r
3
translation is found the physical address of the translation is placed in GR
matching present translation is not found the appropriate TLB fault is taken.
When PSR.dt is 0, only the DTLB is searched, because the VHPT walker is disabled. If no
matching present translation is found in the DTLB, an Alternate Data TLB fault is raised
if psr.ic is one or a Data Nested TLB fault is raised if psr.ic is zero.
If this instruction faults, then it will set the non-access bit in the ISR. The ISR read and
write bits are not set.
This instruction can only be executed at the most privileged level, and when PSR.vm is
0.
Operation:
if (PR[qp]) {
itype = NON_ACCESS|TPA;
check_target_register(r
if (PSR.cpl != 0)
privileged_operation_fault(itype);
if (GR[r
register_nat_consumption_fault(itype);
GR[r ] = tlb_translate_nonaccess(GR[r
1
GR[r ].nat = 0;
1
}
Illegal Operation fault
Interruptions:
Privileged Operation fault
Register NaT Consumption fault
Unimplemented Data Address fault
Virtualization fault
Data Nested TLB fault
3:268
=
r
3
);
1
].nat)
3
is obtained and placed in
r
3
bits {63:61}. If a matching present
r
3
], itype);
3
Alternate Data TLB fault
VHPT Data fault
Data TLB fault
Data Page Not Present fault
Data NaT Page Consumption fault
Volume 3: Instruction Reference
M46
. If a
r
1