Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1794

CMPPS: Packed Single-FP Compare (Continued)
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
Compilers and assemblers should implement the following 2-operand pseudo-ops in
Comments:
addition to the 3-operand CMPPS instruction:
CMPEQPS xmm1, xmm2
CMPLTPS xmm1, xmm2
CMPLEPS xmm1, xmm2
CMPUNORDPS xmm1, xmm2
CMPNEQPS xmm1, xmm2
CMPNLTPS xmm1, xmm2
CMPNLEPS xmm1, xmm2
CMPORDPS xmm1, xmm2
The greater-than relations not implemented in hardware require more than one
instruction to emulate in software and therefore should not be implemented as
pseudo-ops. (For these, the programmer should reverse the operands of the
corresponding less than relations and use move instructions to ensure that the mask is
moved to the correct destination register and that the source operand is left intact.)
Bits 7-4 of the immediate field are reserved. Different processors may handle them
differently. Usage of these bits risks incompatibility with future processors.
4:492
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault
Pseudo-Op
CMPPS xmm1,xmm2, 0
CMPPS xmm1,xmm2, 1
CMPPS xmm1,xmm2, 2
CMPPS xmm1,xmm2, 3
CMPPS xmm1,xmm2, 4
CMPPS xmm1,xmm2, 5
CMPPS xmm1,xmm2, 6
CMPPS xmm1,xmm2, 7
Implementation
Volume 4: IA-32 SSE Instruction Reference