Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1495

FXAM—Examine
Opcode
D9 E5
Description
Examines the contents of the ST(0) register and sets the condition code flags C0, C2,
and C3 in the FPU status word to indicate the class of value or number in the register
(see the table below).
.
Class
Unsupported
NaN
Normal finite number
Infinity
Zero
Empty
Denormal number
The C1 flag is set to the sign of the value in ST(0), regardless of whether the register is
empty or full.
Operation
C1  sign bit of ST; (* 0 for positive, 1 for negative *)
CASE (class of value or number in ST(0)) OF
Unsupported:C3, C2, C0  000;
NaN:
Normal:
Infinity:
Zero:
Empty:
Denormal:
ESAC;
FPU Flags Affected
C1
C0, C2, C3
Floating-point Exceptions
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Volume 4: Base IA-32 Instruction Reference
Instruction
FXAM
C3 C2
0 0
0 0
0 1
0 1
1 0
1 0
1 1
C3, C2, C0  001;
C3, C2, C0  010;
C3, C2, C0  011;
C3, C2, C0  100;
C3, C2, C0  101;
C3, C2, C0  110;
Sign of value in ST(0).
See table above.
Abort.
Description
Classify value or number in ST(0)
C0
0
1
0
1
0
1
0
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