Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1428

FDIVR/FDIVRP/FIDIVR—Reverse Divide (Continued)
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Floating-point Exceptions
#IS
#IA
#D
#Z
#U
#O
#P
Protected Mode Exceptions
#GP(0)
#SS(0)
#NM
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
#SS
#NM
Virtual 8086 Mode Exceptions
#GP(0)
#SS(0)
#NM
#PF(fault-code)
#AC(0)
4:126
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Stack underflow occurred.
Operand is an SNaN value or unsupported format.
; 0 / 0
Result is a denormal value.
SRC / 0, where SRC is not equal to 0.
Result is too small for destination format.
Result is too large for destination format.
Value cannot be represented exactly in destination format.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
EM or TS in CR0 is set.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
EM or TS in CR0 is set.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
EM or TS in CR0 is set.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made.
Volume 4: Base IA-32 Instruction Reference