Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1466

FSAVE/FNSAVE—Store FPU State (Continued)
Virtual 8086 Mode Exceptions
#GP(0)
#SS(0)
#NM
#PF(fault-code)
#AC(0)
Intel Architecture Compatibility Information
For Intel math coprocessors and FPUs prior to the Pentium processor, an FWAIT
instruction should be executed before attempting to read from the memory image
stored with a prior FSAVE/FNSAVE instruction. This FWAIT instruction helps insure that
the storage operation has been completed.
4:164
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
EM or TS in CR0 is set.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made.
Volume 4: Base IA-32 Instruction Reference