Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1148

srlz — Serialize
( ) srlz.i
Format: qp
( ) srlz.d
qp
Instruction serialization (srlz.i) ensures:
Description:
• prior modifications to processor register resources that affect fetching of
subsequent instruction groups are observed,
• prior modifications to processor register resources that affect subsequent execution
or data memory accesses are observed,
• prior memory synchronization (sync.i) operations have taken effect on the local
processor instruction cache,
• subsequent instruction group fetches are re-initiated after srlz.i completes.
The srlz.i instruction must be in an instruction group after the instruction group
containing the operation that is to be serialized. Operations dependent on the
serialization must be in an instruction group after the instruction group containing the
srlz.i.
Data serialization (srlz.d) ensures:
• prior modifications to processor register resources that affect subsequent execution
or data memory accesses are observed.
The srlz.d instruction must be in an instruction group after the instruction group
containing the operation that is to be serialized. Operations dependent on the
serialization must follow the srlz.d, but they can be in the same instruction group as
the srlz.d.
A srlz cannot be used to stall processor data memory references until prior data
memory references, or memory fences are visible or "accepted" by the external
platform.
The following processor resources require a serialize to ensure side-effects are
observed; CRs, PSR, DBRs, IBRs, PMDs, PMCs, RRs, PKRs, TRs and TCs (refer to
Section 3.2, "Serialization" on page 2:17
Operation:
if (PR[qp]) {
if (instruction_form)
instruction_serialize();
else
data_serialize();
}
None
Interruptions:
Volume 3: Instruction Reference
// data_form
for details).
srlz
instruction_form M24
data_form M24
3:249