Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1726
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PCMPEQB/PCMPEQW/PCMPEQD—Packed Compare for Equal (continued)
Operation
IF instruction is PCMPEQB
THEN
IF DEST(7..0) = SRC(7..0)
* Continue comparison of second through seventh bytes in DEST and SRC *
IF DEST(63..56) = SRC(63..56)
ELSE IF instruction is PCMPEQW
THEN
IF DEST(15..0) = SRC(15..0)
* Continue comparison of second and third words in DEST and SRC *
IF DEST(63..48) = SRC(63..48)
ELSE (* instruction is PCMPEQD *)
IF DEST(31..0) = SRC(31..0)
IF DEST(63..32) = SRC(63..32)
FI;
Flags Affected
None:
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
#UD
#NM
#MF
#PF(fault-code)
4:424
THEN DEST(7 0) FFH;
ELSE DEST(7..0) 0;
THEN DEST(63..56) FFH;
ELSE DEST(63..56) 0;
THEN DEST(15..0) FFFFH;
ELSE DEST(15..0) 0;
THEN DEST(63..48) FFFFH;
ELSE DEST(63..48) 0;
THEN DEST(31..0) FFFFFFFFH;
ELSE DEST(31..0) 0;
THEN DEST(63..32) FFFFFFFFH;
ELSE DEST(63..32) 0;
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If a memory operand effective address is outside the CS, DS, ES, FS
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If EM in CR0 is set.
If TS in CR0 is set.
If there is a pending FPU exception.
If a page fault occurs.
®
Volume 4: IA-32 Intel
MMX™ Technology Instruction Reference
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