Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1786

Table 4-8.
Prefix Type
Segment Override
(2EH,36H,3EH,26H,64H,65H)
Repeat Prefix(F3H)
Repeat NE Prefix(F2H)
Lock Prefix (0F0H)
4.11 Reserved Behavior and Software Compatibility
In many register and memory layout descriptions, certain bits are marked as reserved.
When bits are marked as reserved, it is essential for compatibility with future
processors that software treat these bits as having a future, though unknown, effect.
The behavior of reserved bits should be regarded as not only reserved, but
unpredictable. In general, reserved behavior may also be applied in other areas.
Software should follow these guidelines in dealing with reserved behavior:
• Do not depend on the states of any reserved fields when testing the values of
registers which contain such bits. Mask out the reserved fields before testing.
• Do not depend on the states of any reserved fields when storing to memory or to a
register.
• Do not depend on the ability to retain information written into any reserved fields.
• When loading a register, always load the reserved fields with the values indicated in
the documentation, if any, or reload them with values previously read from the
same register.
Note: Avoid any software dependency upon the reserved state/behavior. Depending
upon reserved behavior will make the software dependent upon the unspecified
manner in which the processor handles this behavior and risks incompatibility
with future processors.
4.12 Notations
Besides opcodes, two kinds of notations are found which both describe information
found in the ModR/M byte:
1. /digit: (digit between 0 and 7) indicates that the instruction uses only the r/m
(register and memory) operand. The reg field contains the digit that provides an
extension to the instruction's opcode.
2. /r: indicates that the ModR/M byte of an instruction contains both a register
operand and an r/m operand.
In addition, the following abbreviations are used:
• r32:
• xmm/m128:Indicates a 128-bit multimedia register or a 128-bit memory location.
• xmm/m64: Indicates a 128-bit multimedia register or a 64-bit memory location.
• xmm/m32: Indicates a 128-bit multimedia register or a 32-bit memory location.
• mm/m64:
4:484
Cacheability Control Instruction Behavior with Prefixes
Effect on SSE Instructions
Affects cacheability control instructions with mem. operand
Ignored by cacheability control instruction without mem operand
Reserved and may result in unpredictable behavior.
Reserved and may result in unpredictable behavior.
Generates an invalid opcode exception for all cacheability
instructions.
Intel architecture 32-bit integer register.
Indicates a 64-bit multimedia register or a 64-bit memory location.
Volume 4: IA-32 SSE Instruction Reference