Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1891

INTA (Interrupt Acknowledge) 2:130
Inter-processor Interrupt (IPI) 2:127
Interrupt Acknowledge Cycle 2:130
Interruption Control Registers (CR16-27) 2:36
Interruption Handler 2:537
Interruption Handling 2:543
Interruption Hash Address 2:41
Interruption Instruction Bundle Registers (IIB0-1)
2:42
Interruption Processor Status Register (IPSR) 2:36
Interruption Register State 2:540
Interruption Registers 2:538
Interruption Status Register (ISR) 2:36
Interruption Vector 2:165
Alternate Data TLB 2:178
Alternate Instruction TLB 2:177
Break Instruction 2:185
Data Access Rights 2:191
Data Access-Bit 2:184
Data Key Miss 2:181
Data Nested TLB 2:179
Data TLB 2:176
Debug 2:200
Dirty-Bit 2:182
Disabled FP-Register 2:195
External Interrupt 2:186
Floating-point Fault 2:203
Floating-point Trap 2:204
General Exception 2:192
IA-32 Exception 2:210
IA-32 Intercept 2:211
IA-32 Interrupt 2:212
Instruction Access Rights 2:190
Instruction Access-Bit 2:183
Instruction Key Miss 2:180
Instruction TLB 2:175
Key Permission 2:189
Lower-Privilege Transfer Trap 2:205
NaT Consumption 2:196
Page Not Present 2:188
Single Step Trap 2:208
Speculation 2:198
Taken Branch Trap 2:207
Unaligned Reference 2:201
Unsupported Data Reference 2:202
Virtual External Interrupt 2:187
Virtualization 2:209
Interruption Vector Address 2:35, 2:538
Interruption Vector Table 2:538
Interruptions 2:95, 2:537
Interrupts 2:96, 2:114
External Interrupt Architecture 2:603
Interval Time Counter (ITC) 1:31
Interval Timer Match Register (ITM) 2:32
Interval Timer Offset (ITO) 2:34
Interval Timer Vector (ITV) 2:125
Index for Volumes 1, 2, 3 and 4
INTn Instruction 4:217
INTO Instruction 4:217
invala Instruction 3:146
INVD instructions 4:228
INVLPG Instruction 4:230
IP (Instruction Pointer) 1:27, 1:140
IPI (Inter-processor Interrupt) 2:127
IPSR (Interruption Processor Status Register)
2:36, 2:541
IRET Instruction 4:231
IRETD Instruction 4:231
IRR (External Interrupt Request Registers) 2:125
ISR (Interruption Status Register) 2:36, 2:165,
2:541
Itanium Architecture 1:7
Itanium Instruction Set 1:21
Itanium System Architecture 1:20
Itanium System Environment 1:7, 1:21
ITC (Interval Time Counter) 1:31, 2:32
itc Instruction 3:147
ITIR (Interruption TLB Insertion Register) 2:541
ITM (Interval Time Match Register) 2:32
ITO (Interval Timer Offset) 2:34
itr Instruction 3:149
ITV (Interval Timer Vector) 2:125
IVA (Interruption Vector Address) 2:35, 2:538
IVA-based interruptions 2:95, 2:537
IVR (External Interrupt Vector Register) 2:123
J
J
cc Instruction 4:239
JMP Instruction 4:243
JMPE Instruction 1:111, 2:597, 4:249
K
Kernel Register (KR) 1:29
KR (Kernel Register) 1:29
L
LAHF Instruction 4:251
Lamport's Algorithm 2:530
LAR Instruction 4:252
Large Constants 1:53
LC (Loop Count Register) 1:33
ld Instruction 3:151
ldf Instruction 3:157
ldfp Instruction 3:161
LDMXCSR Instruction 4:516
LDS Instruction 4:255
LEA Instruction 4:258
LEAVE Instruction 4:260
LES Instruction 4:255
lfetch Instruction 3:164
LFS Instruction 4:255
LGDT Instruction 4:264
INDEX
Index:5