Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1259

Table 4-66.
Opcode
Bits
40:37
4
The floating-point class instructions are encoded within major opcode 5 using a 1-bit
opcode extension field in bit 12 (t
Table 4-67.
Opcode
Bits 40:37
4.6.3.1 Floating-point Compare
40
F4
Instruction
fcmp.eq. sf
fcmp.lt. sf
fcmp.le. sf
fcmp.unord. sf
fcmp.eq.unc. sf
fcmp.lt.unc. sf
fcmp.le.unc. sf
fcmp.unord.unc. sf
4.6.3.2 Floating-point Class
40
F5
fclass.m
fclass.m.unc
3:360
Floating-point Compare Opcode Extensions
r r
a b
Bit 33 Bit 36
0 fcmp.eq
0
1
0
1
1 fcmp.unord
Floating-point Class 1-bit Opcode Extensions
t
a
Bit 12
0
5
1
37 36 35 34 33 32
4 r sf r p
b a 2
4 1 2 1 6
Operands
p , p = f
1 2
37 36 35 34 33 32
5 fc p
2 2
4 2 2 6
Instruction
p , p
1
t
a
Bit 12
0
F4 fcmp.eq.unc
fcmp.lt F4 fcmp.lt.unc
fcmp.le F4 fcmp.le.unc
F4 fcmp.unord.unc
) as shown in Table
a
fclass.m F5
fclass.m.unc
27 26 20 19
f
3
7
Opcode
r
a
0
1
, f 4
2 3
0
1
27 26 20 19
fclass
7c
7
Operands
= f , fclass
2 2 9
1
F4
F4
F4
F4
4-67.
F5
13 12 11 6 5
f t p
2 a 1
7 1 6
Extension
r t sf
b a
0
1
0
0
1
See Table 4-63
on page 3:358
0
1
1
0
1
13 12 11 6 5
f t p
2 a 1
7 1 6
Extension
Opcode
t
a
0
5
1
Volume 3: Instruction Formats
0
qp
6
0
qp
6