Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1772

The CVTPI2PS (Convert packed 32-bit integer to packed single-precision floating-point)
instruction converts two 32-bit signed integers in a MMX technology register to the two
least significant single-precision floating-point numbers; when the conversion is
inexact, the rounded value according to the rounding mode in MXCSR is returned. The
upper two significant numbers in the destination register are retained.
The CVTSI2SS (Convert scalar 32-bit integer to scalar single-precision floating-point)
instruction converts a 32-bit signed integer in a MMX technology register to the least
significant single-precision floating-point number; when the conversion is inexact, the
rounded value according to the rounding mode in MXCSR is returned. The upper three
significant numbers in the destination register are retained.
The CVTPS2PI (Convert packed single-precision floating-point to packed 32-bit integer)
instruction converts the two least significant single-precision floating-point numbers to
two 32-bit signed integers in a MMX technology register; when the conversion is
inexact, the rounded value according to the rounding mode in MXCSR is returned. The
CVTTPS2PI (Convert truncate packed single-precision floating-point to packed 32-bit
integer) instruction is similar to CVTPS2PI except if the conversion is inexact, in which
case the truncated result is returned.
The CVTSS2SI (Convert scalar single-precision floating-point to a 32-bit integer)
instruction converts the least significant single-precision floating-point number to a
32-bit signed integer in an Intel architecture 32-bit integer register; when the
conversion is inexact, the rounded value according to the rounding mode in MXCSR is
returned.The CVTTSS2SI (Convert truncate scalar single-precision floating-point to
scalar 32-bit integer) instruction is similar to CVTSS2SI except if the conversion is
inexact, the truncated result is returned.
4.6.1.6 Data Movement Instructions
The MOVAPS (Move aligned packed single-precision floating-point) instruction transfers
128-bits of packed data from memory to SSE registers and vice versa, or between SSE
registers. The memory address is aligned to 16-byte boundary; if not then a general
protection exception will occur.
The MOVUPS (Move unaligned packed single-precision floating-point) instruction
transfers 128-bits of packed data from memory to SSE registers and vice versa, or
between SSE registers. No assumption is made for alignment.
The MOVHPS (Move aligned high packed single-precision floating-point) instruction
transfers 64-bits of packed data from memory to the upper two fields of a SSE register
and vice versa. The lower field is left unchanged.
The MOVLPS (Move aligned low packed single-precision floating-point) instruction
transfers 64-bits of packed data from memory to the lower two fields of a SSE register
and vice versa. The upper field is left unchanged.
The MOVMSKPS (Move mask packed single-precision floating-point) instruction
transfers the most significant bit of each of the four packed single-precision
floating-point number to an IA integer register. This 4-bit value can then be used as a
condition to perform branching.
4:470 Volume 4: IA-32 SSE Instruction Reference