Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1671

SMSW—Store Machine Status Word
Opcode
0F 01 /4
Description
Stores the machine status word (bits 0 through 15 of control register CR0) into the
destination operand. The destination operand can be a 16-bit general-purpose register
or a memory location.
When the destination operand is a 32-bit register, the low-order 16 bits of register CR0
are copied into the low-order 16 bits of the register and the upper 16 bits of the register
are undefined. With the destination operand is a memory location, the low-order 16 bits
of register CR0 are written to memory as a 16-bit quantity, regardless of the operand
size.
The SMSW instruction is only useful in operating-system software; however, it is not a
privileged instruction and can be used in application programs.
This instruction is provided for compatibility with the Intel 286 processor; programs and
procedures intended to run on processors more recent than the Intel 286 should use
the MOV (control registers) instruction to load the machine status word.
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,SMSW);
DEST  CR0[15:0]; (* MachineStatusWord *);
Flags Affected
None.
Additional Itanium System Environment Exceptions
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Volume 4: Base IA-32 Instruction Reference
Instruction Description
SMSW r32/m16 Store machine status word in low-order 16 bits of r32/m16 ;
high-order 16 bits of r32 are undefined
Mandatory Instruction Intercept.
If the destination is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
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