Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1551

JMPE—Jump to Intel
Opcode
0F 00 /6
0F 00 /6
0F B8
0F B8
Description
This instruction is available only on processors based on the Itanium architecture in the
Itanium System Environment. Otherwise, execution of this instruction at privilege levels
1, 2, and 3 results in an Illegal Opcode fault, and at privilege level 0, termination of the
IA-32 System Environment on a processor based on the Itanium architecture.
JMPE switches the processor to the Itanium instruction set and starts execution at the
specified target address There are two forms; an indirect form, r/mr16/32, and an
unsigned absolute form, disp16/32. Both 16 and 32-bit formats are supported.
The absolute form computes the 16-byte aligned 64-bit virtual target address in the
Itanium instruction set by adding the unsigned 16 or 32-bit displacement to the current
CS base (IP{31:0} = disp16/32 + CSD.base). The indirect form specifies the virtual
target address by the contents of a register or memory location (IP{31:0} =
[r/m16/32] + CSD.base). Target addresses are constrained to the lower 4G-bytes of
the 64-bit virtual address space within virtual region 0.
GR[1] is loaded with the next sequential instruction address following JMPE.
If PSR.di is 1, the instruction is nullified and a Disabled Instruction Set Transition fault is
generated. If Itanium branch debugging is enabled, an IA_32_Exception(Debug)
trap is taken after JMPE completes execution.
JMPE can be performed at any privilege level and does not change the privilege level of
the processor.
JMPE performs a FWAIT operation, any pending IA-32 unmasked floating-point
exceptions are reported as faults on the JMPE instruction.
JMPE does not perform a memory fence or serialization operation.
Successful execution of JMPE clears EFLAG.rf and PSR.id to zero.
If the register stack engine is enabled for eager execution, the register stack engine
may immediately start loading registers when the processor enters the Itanium
instruction set.
Volume 4: Base IA-32 Instruction Reference
® ®
Itanium Instruction Set
Instruction Description
JMPE r/m16 Jump to Intel Itanium instruction set, indirect address specified by
r/m16
JMPE r/m32 Jump to Intel Itanium instruction set, indirect address specified by
r/m32
JMPE disp16 Jump to Intel Itanium instruction set, absolute address specified by
addr16
JMPE disp32 Jump to Intel Itanium instruction set, absolute address specified by
addr32
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