Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1377

CMPXCHG—Compare and Exchange (Continued)
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
#SS
Virtual 8086 Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Intel Architecture Compatibility
This instruction is not supported on Intel processors earlier than the Intel486
processors.
Volume 4: Base IA-32 Instruction Reference
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Lock Intercept If an external atomic bus lock is required to
–
complete this operation and DCR.lc is 1, no atomic transaction
occurs, this instruction is faulted and an IA-32_Intercept(Lock) fault
is generated. The software lock handler is responsible for the
emulation of this instruction.
If the destination is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made.
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