Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1200

Table 4-9.
Opcode
Bits
40:37
8
4.2.1.1 Integer ALU – Register-Register
40
A1
Instruction
add
sub
addp4
and
andcm
or
xor
4.2.1.2 Shift Left and Add
40
A2
Instruction
shladd
shladdp4
Volume 3: Instruction Formats
Integer ALU 4-bit+2-bit Opcode Extensions
x v x
2a e 4
Bits Bit Bits
35:34 33 32:29
0 add
1 sub -1
2 addp4
3 and
4
5
6
7
0 0
8
9
A
B and – imm
C
D
E
F
37 36 35 34 33 32 29 28 27 26
8 x v x x
2a e 4 2b
4 1 2 1 4 2
Operands
r = r , r
1 2 3
r = r , r , 1
1 2 3
r = r , r
1 2 3
r = r , r , 1
1 2 3
r = r , r
1 2 3
37 36 35 34 33 32 29 28 27 26
8 x v x ct
2a e 4
4 1 2 1 4 2
Operands
r = r , count , r
1 2 2 3
Bits 28:27
0 1
A1 add +1 A1
A1 sub A1
A1
A1 andcm A1
shladd
shladdp4
sub – imm A3
8
A3 andcm – imm
8 8
20 19
r r
3 2
7 7
Opcode
x
2a
8 0
20 19
r r
2d 3 2
7 7
Opcode
8
x
2b
2
or A1
A2
A2
A3 or – imm A3 xor – imm
8
13 12 6 5
r
1
7
Extension
v x x
e 4
0
1
0 2
3
13 12 6 5
r
1
7
Extension
x v x
2a e 4
4
0 0
6
3
xor A1
A3
8
0
qp
6
2b
0
1
1
0
0
0
1
2
3
0
qp
6
3:301