Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1150

st — Store
( ) st .
Format: qp sz sttype
( ) st .
qp sz sttype
( ) st16.
qp sttype
( ) st8.spill.
qp
( ) st8.spill.
qp
A value consisting of the least significant sz bytes of the value in GR
Description:
memory starting at the address specified by the value in GR
completer are given in
store operations, which are described in
is 1, or in sixteen_byte_form or normal_form, if the NaT bit corresponding to GR
r
3
1, a Register NaT Consumption fault is taken.
In the sixteen_byte_form, two 8-byte values are stored as a single, 16-byte atomic
memory write. The value in GR
by the value in GR
(AR[CSD]) is written to memory starting at the address specified by the value in GR
plus 8.
In the spill_form, an 8-byte value is stored, and the NaT bit corresponding to GR
copied to a bit in the UNAT application register. This instruction is used for spilling a
register/NaT pair. See
In the imm_base_update form, the value in GR
( ) and the result is placed back in GR
imm
9
store, and does not affect the store address, nor the value stored (for the case where
and specify the same register). Base register update is not supported for the st16
r
3
instruction.
Table 2-50.
sttype
Completer
none
rel
For more details on ordered stores see
page 1:73.
The ALAT is queried using the physical memory address and the access size, and all
overlapping entries are invalidated.
The value of the sthint completer specifies the locality of the memory access. The values
of the sthint completer are given in
update forms. The address specified by the value in GR
a hint to prefetch the indicated cache line. This prefetch uses the locality hints specified
by sthint. See
page 1:69.
Hardware support for st16 instructions that reference a page that is neither a
cacheable page with write-back policy nor a NaTPage is optional. On processor models
that do not support such st16 accesses, an Unsupported Data Reference fault is raised
when an unsupported reference is attempted.
Volume 3: Instruction Reference
. [ ] =
sthint r r
3 2
. [ ] = ,
sthint r r imm
3 2 9
. [ ] = , ar.csd
sthint r r
3 2
[ ] =
sthint r r
3 2
[ ] = ,
sthint r r imm
3 2 9
Table 2-32 on page
is written to memory starting at the address specified
r
2
. The value in the Compare and Store Data application register
r
3
Section 4.4.4, "Control Speculation" on page 1:60
Store Types
Interpretation
Normal store
Ordered store An ordered store is performed with release semantics.
Section 4.4.6, "Memory Hierarchy Control and Consistency" on
normal_form, no_base_update_form
normal_form, imm_base_update_form
sixteen_byte_form, no_base_update_form
spill_form, no_base_update_form
spill_form, imm_base_update_form
3:151. The sttype completer specifies special
Table 2-50. If the NaT bit corresponding to GR
is added to a signed immediate value
r
3
. This base register update is done after the
r
3
Special Store Operation
Section 4.4.7, "Memory Access Ordering" on
Table 2-51. A prefetch hint is implied in the base
after the base update acts as
r
3
is written to
r
2
. The values of the sz
r
3
r
2
is
r
2
for details.
3:251
st
M6
M5
M6
M6
M5
is
r
3
r
2