Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1478

FSTCW/FNSTCW—Store Control Word
Opcode
9B D9 /7
D9 /7
Description
Stores the current value of the FPU control word at the specified destination in memory.
The FSTCW instruction checks for and handles pending unmasked floating-point
exceptions before storing the control word; the FNSTCW instruction does not.
Operation
DEST  FPUControlWord;
FPU Flags Affected
The C0, C1, C2, and C3 flags are undefined.
Floating-point Exceptions
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
#NM
#PF(fault-code)
#AC(0)
4:176
Instruction Description
FSTCW m2byte Store FPU control word to m2byte after checking for pending
unmasked floating-point exceptions.
FNSTCW m2byte Store FPU control word to m2byte without checking for pending
unmasked floating-point exceptions.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If the destination is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
EM or TS in CR0 is set.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Volume 4: Base IA-32 Instruction Reference