Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1749

PSUBB/PSUBW/PSUBD—Packed Subtract (continued)
Note that like the integer SUB instruction, the PSUBB, PSUBW, and PSUBD instructions
can operate on either unsigned or signed (two's complement notation) packed integers.
Unlike the integer instructions, none of the MMX technology instructions affect the
EFLAGS register. With MMX technology instructions, there are no carry or overflow flags
to indicate when overflow has occurred, so the software must control the range of
values or else use the "with saturation" MMX technology instructions.
Operation
IF instruction is PSUBB
THEN
DEST(7..0)  DEST(7..0) - SRC(7..0);
DEST(15..8)  DEST(15..8) - SRC(15..8);
DEST(23..16)  DEST(23..16) - SRC(23..16);
DEST(31..24)  DEST(31..24) - SRC(31..24);
DEST(39..32)  DEST(39..32) - SRC(39..32);
DEST(47..40)  DEST(47..40) - SRC(47..40);
DEST(55..48)  DEST(55..48) - SRC(55..48);
DEST(63..56)  DEST(63..56) - SRC(63..56);
ELSEIF instruction is PSUBW
THEN
DEST(15..0)  DEST(15..0) - SRC(15..0);
DEST(31..16)  DEST(31..16) - SRC(31..16);
DEST(47..32)  DEST(47..32) - SRC(47..32);
DEST(63..48)  DEST(63..48) - SRC(63..48);
ELSE { (* instruction is PSUBD *)
DEST(31..0)  DEST(31..0) - SRC(31..0);
DEST(63..32)  DEST(63..32) - SRC(63..32);
FI;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
®
Volume 4: IA-32 Intel MMX™ Technology Instruction Reference
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
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