Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1881

MOVNTQ: Move 64 Bits Non-temporal
Opcode
0F,E7,/r
Operation: m64 = mm;
The linear address corresponds to the address of the least-significant byte of the
Description:
referenced memory data. This store instruction minimizes cache pollution.
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF (fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a pending FPU
exception; #AC for unaligned memory reference. To enable #AC exceptions, three
conditions must be true(CR0.AM is set; EFLAGS.AC is set; current CPL is 3).
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a
pending FPU exception.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #AC for unaligned memory reference if the
current privilege level is 3; #PF (fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
MOVNTQ minimizes pollution in the cache hierarchy. As a consequence of the resulting
Comments:
weakly-ordered memory consistency model, a fencing operation should be used if
multiple processors may use different memory types to read/write the memory
location. See Section 4.6.1.9, "Cacheability Control Instructions" for further information
about non-temporal stores.
MOVNTQ ignores the value of CR4.OSFXSR. Since it does not affect the new SSE state,
they will not generate an invalid exception if CR4.OSFXSR = 0.
Volume 4: IA-32 SSE Instruction Reference
Instruction
MOVNTQ m64, mm
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault, Data Dirty Bit Fault
Description
Move 64 bits representing integer operands (8b, 16b, 32b) from
MM register to memory, minimizing pollution within cache
hierarchy.
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