Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1574

LOCK—Assert LOCK# Signal Prefix
Opcode
F0
Description
Causes the processor's LOCK# signal to be asserted during execution of the
accompanying instruction (turns the instruction into an atomic instruction). In a
multiprocessor environment, the LOCK# signal insures that the processor has exclusive
use of any shared memory while the signal is asserted.
The LOCK prefix can be prepended only to the following instructions and to those forms
of the instructions that use a memory operand: ADD, ADC, AND, BTC, BTR, BTS,
CMPXCHG, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. An undefined
opcode exception will be generated if the LOCK prefix is used with any other instruction.
The XCHG instruction always asserts the LOCK# signal regardless of the presence or
absence of the LOCK prefix.
The LOCK prefix is typically used with the BTS instruction to perform a
read-modify-write operation on a memory location in shared memory environment.
The integrity of the LOCK prefix is not affected by the alignment of the memory field.
Memory locking is observed for arbitrarily misaligned fields.
Operation
IF Itanium System Environment AND External_Bus_Lock_Required AND DCR.lc
THEN IA-32_Intercept(LOCK);
AssertLOCK#(DurationOfAccompaningInstruction)
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
IA-32_Intercept
Protected Mode Exceptions
#UD
4:272
Instruction Description
LOCK Asserts LOCK# signal for duration of the accompanying
instruction
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Lock Intercept If an external atomic bus lock is required to
–
complete this operation and DCR.lc is 1, no atomic transaction
occurs, the instruction is faulted and an IA-32_Intercept(Lock) fault
is generated. The software lock handler is responsible for the
emulation of the instruction.
If the LOCK prefix is used with an instruction not listed in the
"Description" section above. Other exceptions can be generated by
the instruction that the LOCK prefix is being applied to.
Volume 4: Base IA-32 Instruction Reference