Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 911

(64-bits not including the NaT bit) where the notation GR[addr] is used. The syntactical
differences between the code found in the Operation section and ANSI C is listed in
Table 2-4.
Table 2-3.
Application registers
Branch registers
Control registers
CPU identification registers
Data breakpoint registers
Instruction breakpoint registers
Data TLB translation cache
Data TLB translation registers
Floating-point registers
General registers
Instruction TLB translation cache
Instruction TLB translation registers
Protection key registers
Performance monitor configuration registers
Performance monitor data registers
Predicate registers
Region registers
Table 2-4.
Syntax
{msb:lsb}, {bit}
u>, u>=, u<, u<=
u>>, u>>=
u+
u*
The Operation section contains code that specifies only the execution semantics of each
instruction and does not include any behavior relating to instruction fetch (e.g.,
interrupts and faults caused during fetch). The Interruptions section does not list any
faults that may be caused by instruction fetch or by mandatory RSE loads. The code to
raise certain pervasive faults and actions is not included in the code in the Operation
section. These faults and actions are listed in
all instructions and is not listed in the Interruptions section.
3:12
Register File Notation
Register File
C Syntax Differences
Bit field specifier. When appended to a variable, denotes a bit field extending from the
most significant bit specified by "msb" to the least significant bit specified by "lsb"
including bits "msb" and "lsb." If "msb" and "lsb" are equal then a single bit is
accessed. The second form denotes a single bit.
Unsigned inequality relations. Variables on either side of the operator are treated as
unsigned.
Unsigned right shift. Zeroes are shifted into the most significant bit position.
Unsigned addition. Operands are treated as unsigned, and zero-extended.
Unsigned multiplication. Operands are treated as unsigned.
Assembly
C Notation
Mnemonic
AR ar
BR b
CR cr
CPUID cpuid
DBR dbr
IBR ibr
DTC N/A
DTR dtr
FR f
GR r
ITC N/A
ITR itr
PKR pkr
PMC pmc
PMD pmd
PR p
RR rr
Function
Table 2-5. The Single step trap applies to
Volume 3: Instruction Reference
Indirect
Access
Y
Y
Y
Y
Y
Y
Y
Y
Y