Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1735

PMULLW—Packed Multiply Low
Opcode
0F D5 /r
Description
Multiplies the four signed or unsigned words of the source operand (second operand)
with the four signed or unsigned words of the destination operand (first operand),
producing four doubleword, intermediate results (see
of each intermediate result is then written to its corresponding word location in the
destination operand. The destination operand must be an MMX technology register; the
source operand may be either an MMX technology register or a 64-bit memory location.
Figure 3-14.
mm
mm/m64
mm
Operation
DEST(15..0)  LowOrderWord(DEST(15..0)  SRC(15..0));
DEST(31..16)  LowOrderWord(DEST(31..16)  SRC(31..16));
DEST(47..32)  LowOrderWord(DEST(47..32)  SRC(47..32));
DEST(63..48)  LowOrderWord(DEST(63..48)  SRC(63..48));
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
®
Volume 4: IA-32 Intel MMX™ Technology Instruction Reference
Instruction
PMULLW mm,
mm/m64
Operation of the PMULLW Instruction
PMULLW mm, mm/m64
*
Low Order Low Order
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Description
Multiply the packed words in mm with the packed words in
mm/m64 , then store the low-order word of each doubleword
result in mm .
Figure
0111000111000111
* *
1000000000000000
Low Order
1000000000000000
3-14). The low-order word
0111000111000111
*
0000010000000000
Low Order
0001110000000000
3006025
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