Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1530

INVD—Invalidate Internal Caches
Opcode
0F 08
Description
Invalidates (flushes) the processor's internal caches and issues a special-function bus
cycle that directs external caches to also flush themselves. Data held in internal caches
is not written back to main memory.
After executing this instruction, the processor does not wait for the external caches to
complete their flushing operation before proceeding with instruction execution. It is the
responsibility of hardware to respond to the cache flush signal.
The INVD instruction is a privileged instruction. When the processor is running in
protected mode, the CPL of a program or procedure must be 0 to execute this
instruction. This instruction is also implementation-dependent; its function may be
implemented differently on future Intel architecture processors.
Use this instruction with care. Data cached internally and not written back to main
memory will be lost. Unless there is a specific requirement or benefit to flushing caches
without writing back modified cache lines (for example, testing or fault recovery where
cache coherency with main memory is not a concern), software should use the WBINVD
instruction.
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,INVD);
Flush(InternalCaches);
SignalFlush(ExternalCaches);
Continue (* Continue execution);
Flags Affected
None.
Additional Itanium System Environment Exceptions
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
Real Address Mode Exceptions
None.
Virtual 8086 Mode Exceptions
#GP(0)
4:228
Instruction Description
INVD Flush internal caches; initiate flushing of external caches.
Mandatory Instruction Intercept
If the current privilege level is not 0.
The INVD instruction cannot be executed at the virtual 8086 mode.
Volume 4: Base IA-32 Instruction Reference