Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1185

Table 3-1. Pseudo-code Functions (Continued)
Function
mem_xchg_add(add_val, paddr, size,
byte_order, mattr, otype, hint)
mem_xchg_cond(cmp_val, data, paddr,
size, byte_order, mattr, otype, hint)
mem_xchg16_cond(cmp_val, gr_data,
ar_data, paddr, byte_order, mattr, otype,
hint)
ordering_fence()
partially_implemented_ip()
pending_virtual_interrupt()
pr_phys_to_virt(phys_id)
rotate_regs()
rse_enable_current_frame_load()
rse_ensure_regs_loaded(number_of_byt
es)
rse_invalidate_non_current_regs()
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Intel Itanium Architecture Software Developer's Manual Rev. 2.3
Returns size bytes from memory starting at the physical address specified by
paddr . The read is conditioned by the locality hint specified by hint . The least
significant size bytes of the sum of the value read from memory and add_val is
then written to size bytes in memory starting at the physical address specified by
paddr . The read and write are performed atomically. Both the read and the write are
conditioned by the memory attribute specified by mattr and the byte ordering in
memory is specified by byte_order . otype specifies the memory ordering attribute
of this access, and has the value ACQUIRE or RELEASE.
Returns size bytes from memory starting at the physical address specified by
paddr . The read is conditioned by the locality hint specified by hint . If the value read
from memory is equal to cmp_val, then the least significant size bytes of data are
written to size bytes in memory starting at the physical address specified by
paddr . If the write is performed, the read and write are performed atomically. Both the
read and the write are conditioned by the memory attribute specified by mattr and
the byte ordering in memory is specified by byte_order . otype specifies the
memory ordering attribute of this access, and has the value ACQUIRE or RELEASE.
Returns 8 bytes from memory starting at the physical address specified by paddr .
The read is conditioned by the locality hint specified by hint . If the value read from
memory is equal to cmp_val , then the 8 bytes of gr_data are written to 8 bytes in
memory starting at the physical address specified by ( paddr & ~0x8), and the 8 bytes
of ar_data are written to 8 bytes in memory starting at the physical address
specified by (( paddr & ~0x8) + 8). If the write is performed, the read and write are
performed atomically. Both the read and the write are conditioned by the memory
attribute specified by mattr and the byte ordering in memory is specified by
byte_order . The byte ordering only affects the ordering of bytes within each of the
8-byte values stored. otype specifies the memory ordering attribute of this access,
and has the value ACQUIRE or RELEASE.
Ensures prior data memory references are made visible before future data memory
references are made visible by the processor.
Implementation-dependent routine which returns TRUE if the implementation, on an
Unimplemented Instruction Address trap, writes IIP with the sign-extended virtual
address or zero-extended physical address for what would have been the next value
of IP. Returns FALSE if the implementation, on this trap, simply writes IIP with the full
address which would have been the next value of IP.
Check for unmasked pending virtual interrupt.
Returns the virtual register id of the predicate from the physical register id, phys_id
of the predicate.
Decrements the Register Rename Base registers, effectively rotating the register
files. CFM.rrb.gr is decremented only if CFM.sor is non-zero.
If the RSE load pointer (RSE.BSPLoad) is greater than AR[BSP], the RSE.CFLE bit is
set to indicate that mandatory RSE loads are allowed to restore registers in the
current frame (in no other case does the RSE spill or fill registers in the current
frame). This function does not perform mandatory RSE loads. This procedure does
not cause any interruptions.
All registers and NaT collections between AR[BSP] and
(AR[BSP]-number_of_bytes) which are not already in stacked registers are
loaded into the register stack with mandatory RSE loads. If the number of registers to
be loaded is greater than RSE.N_STACK_PHYS an Illegal Operation fault is raised. All
registers starting with backing store address (AR[BSP] - 8) and decrementing down
to and including backing store address (AR[BSP] - number_of_bytes) are made part
of the dirty partition. With exception of the current frame, all other stacked registers
are made part of the invalid partition. Note that number_of_bytes may be zero. The
resulting sequence of RSE loads may be interrupted. Mandatory RSE loads may
cause an interruption; see Table 6-6, "RSE Interruption Summary" on page
All registers outside the current frame are invalidated.
Operation
Volume 3: Pseudo-Code Functions
6-145.