Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1164

thash — Translation Hashed Entry Address
( ) thash
Format: qp
A Virtual Hashed Page Table (VHPT) entry address is generated based on the specified
Description:
virtual address and the result is placed in GR
and the region register selected by GR
If thash is given a NaT input argument or an unimplemented virtual address as an
input, the resulting target register value is undefined, and its NaT bit is set to one.
When the processor is configured to use the region-based short format VHPT
(PTA.vf=0), the value returned by thash is defined by the architected short format
hash function. See
When the processor is configured to use the long format VHPT (PTA.vf=1), thash
performs an implementation-specific long format hash function on the virtual address
to generate a hash index into the long format VHPT.
In the long format, a translation in the VHPT must be uniquely identified by its hash
index generated by this instruction and the hash tag produced from the ttag
instruction.
The hash function must use all implemented region bits and only virtual address bits
{60:0} to determine the offset into the VHPT. Virtual address bits {63:61} are used
only by the short format hash to determine the region of the VHPT.
This instruction must be implemented on all processor models, even processor models
that do not implement a VHPT walker.
This instruction can only be executed when PSR.vm is 0.
Operation:
if (PR[qp]) {
check_target_register(r
if (PSR.vm == 1)
virtualization_fault();
if (GR[r
GR[r
GR[r
} else {
tmp_vr = GR[r
tmp_va = GR[r
GR[r
GR[r
}
}
Illegal Operation fault
Interruptions:
Volume 3: Instruction Reference
=
r r
1 3
Section 4.1.5.3, "Region-based VHPT Short Format" on page
);
1
].nat || unimplemented_virtual_address(GR[r
3
] = undefined();
1
].nat = 1;
1
]{63:61};
3
]{60:0};
3
] = tlb_vhpt_hash(tmp_vr, tmp_va, RR[tmp_vr].rid,
1
RR[tmp_vr].ps);
].nat = 0;
1
. The virtual address is specified by GR
r
1
bits {63:61}.
r
3
Virtualization fault
thash
M46
r
3
2:63.
], PSR.vm)) {
3
3:265