Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1687

VERR, VERW—Verify a Segment for Reading or Writing (Continued)
Flags Affected
The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable
(VERW); otherwise, it is cleared to 0.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
The only exceptions generated for these instructions are those related to illegal
addressing of the source operand.
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#UD
Virtual 8086 Mode Exceptions
#UD
Volume 4: Base IA-32 Instruction Reference
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
The VERR and VERW instructions are not recognized in real address
mode.
The VERR and VERW instructions are not recognized in virtual 8086
mode.
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