Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1007

fpma
Operation: if (PR[qp]) {
fp_check_target_register(f
if (tmp_isrcode = fp_reg_disabled(f
disabled_fp_register_fault(tmp_isrcode, 0);
if (fp_is_natval(FR[f
fp_is_natval(FR[f
FR[f
fp_update_psr(f
} else {
tmp_default_result_pair = fpma_exception_fault_check(f
if (fp_raise_fault(tmp_fp_env))
if (fp_is_nan_or_inf(tmp_default_result_pair.hi)) {
} else {
}
if (fp_is_nan_or_inf(tmp_default_result_pair.lo)) {
} else {
}
FR[f
FR[f
FR[f
fp_update_fpsr(sf, tmp_fp_env);
fp_update_psr(f
if (fp_raise_traps(tmp_fp_env))
}
}
Invalid Operation (V)
FP Exceptions:
Denormal/Unnormal Operand (D)
Software Assist (SWA) Fault
Illegal Operation fault
Interruptions:
Disabled Floating-point Register fault
3:108
);
1
]) || fp_is_natval(FR[f
2
])) {
4
] = NATVAL;
1
);
1
fp_exception_fault(fp_decode_fault(tmp_fp_env));
tmp_res_hi = fp_single(tmp_default_result_pair.hi);
tmp_res = fp_mul(fp_reg_read_hi(f
if (f != 0)
2
tmp_res = fp_add(tmp_res, fp_reg_read_hi(f
tmp_res_hi = fp_ieee_round_sp(tmp_res, HIGH, &tmp_fp_env);
tmp_res_lo = fp_single(tmp_default_result_pair.lo);
tmp_res = fp_mul(fp_reg_read_lo(f
if (f != 0)
2
tmp_res = fp_add(tmp_res, fp_reg_read_lo(f
tmp_res_lo = fp_ieee_round_sp(tmp_res, LOW, &tmp_fp_env);
].significand = fp_concatenate(tmp_res_hi, tmp_res_lo);
1
].exponent = FP_INTEGER_EXP;
1
].sign = FP_SIGN_POSITIVE;
1
);
1
fp_exception_trap(fp_decode_trap(tmp_fp_env));
, f , f , f ))
1 2 3 4
]) ||
3
f , f , sf, &tmp_fp_env);
3 4
), fp_reg_read_hi(f
3
), tmp_fp_env);
2
), fp_reg_read_lo(f
3
), tmp_fp_env);
2
Underflow (U)
Overflow (O)
Inexact (I)
Software Assist (SWA) trap
Floating-point Exception fault
Floating-point Exception trap
Volume 3: Instruction Reference
,
2
));
4
));
4