Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1784

Table 4-4.
Data Type
Single-precision
Table 4-5
denormalized-finite, normalized-finite, and ) and NaNs for the single-real data-type. It
also gives the format for the real indefinite value, which is a QNaN encoding that is
generated by several SSE instructions in response to a masked floating-point
invalid-operation exception.
Table 4-5.
Positive
Negative
NaNs
When storing real values in memory, single-real values are stored in 4 consecutive
bytes in memory. The 128-bit access mode is used for 128-bit memory accesses,
128-bit transfers between SSE registers, and all logical, unpack and arithmetic
instructions.The 32-bit access mode is used for 32-bit memory access, 32-bit transfers
between SSE registers, and all arithmetic instructions.
There are sixty-eight new instructions in SSE instruction set. This chapter describes the
packed and scalar floating-point instructions in alphabetical order, with a full description
of each instruction. The last two sections of this chapter describe the SIMD Integer
instructions and the cacheability control instructions.
4:482
Precision and Range of SSE Datatype
Length
32
shows the encodings for all the classes of real numbers (that is, zero,
Real Number and NaN Encodings
Class Sign
+ 
0
+Normals 0
0
+Denormals 0
0
+Zero 0
 Zero
1
 Denormals
1
1
 Normals
1
1
- 
1
SNaN X
QNaN X
Real Indefinite 1
(QNaN)
Single
Approximate Normalized Range
Precision
(Bits)
Binary
-126
24 2 to 2
Biased Exponent
11..11
11..10
. .
. .
00..01
00..00
. .
. .
00..00
00..00
00..00
00..00
. .
. .
00..00
00..01
. .
. .
11..10
11..11
11..11
11..11
11..11
 8 Bits 
Volume 4: IA-32 SSE Instruction Reference
Decimal
-
127 1.18  10 38 to 3.40  10
Significand
1
Integer Fraction
1
1
.
.
1
0
.
.
0
0
0
0
.
.
0
1
.
.
1
1
1 0X..XX
1 1X..XX
1
 23 Bits 
38
00..00
11..11
.
.
00..00
11.11
.
.
00..01
00..00
00..00
00..01
.
.
11..11
00..00
.
.
11..11
00..00
2
10..00