Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1883

SFENCE: Store Fence
Opcode
0F AE /7
Operation: while (!(preceding_stores_globally_visible)) wait();
Weakly ordered memory types can enable higher performance through such techniques
Description:
as out-of-order issue, write-combining, and write-collapsing. Memory ordering issues
can arise between a producer and a consumer of data and there are a number of
common usage models which may be affected by weakly ordered stores: (1) library
functions, which use weakly ordered memory to write results (2) compiler-generated
code, which also benefit from writing weakly-ordered results, and (3) hand-written
code. The degree to which a consumer of data knows that the data is weakly ordered
can vary for these cases. As a result, the SFENCE instruction provides a
performance-efficient way of ensuring ordering between routines that produce
weakly-ordered results and routines that consume this data.
SFENCE uses the following ModRM encoding:
Mod (7:6) = 11B
Reg/Opcode (5:3) = 111B
R/M (2:0) = 000B
All other ModRM encodings are defined to be reserved, and use of these encodings risks
incompatibility with future processors.
None
Numeric Exceptions:
Protected Mode Exceptions:
Real Address Mode Exceptions:
Virtual 8086 Mode Exceptions:
Additional Itanium System Environment Exceptions: None
SFENCE ignores the value of CR4.OSFXSR. SFENCE will not generate an invalid
Comments:
exception if CR4.OSFXSR = 0
Volume 4: IA-32 SSE Instruction Reference
Instruction
SFENCE
None
None
None
Description
Guarantees that every store instruction that precedes in
program order the store fence instruction is globally visible
before any store instruction which follows the fence is globally
visible.
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