Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1180

Pseudo-Code Functions
3
This chapter contains a table of all pseudo-code functions used on the Itanium
instruction pages.
Table 3-1. Pseudo-code Functions
Function
xxx _fault(parameters ...)
xxx _trap(parameters ...)
acceptance_fence()
alat_cmp(rtype, raddr)
alat_frame_update( delta_bof, delta_sof)
alat_inval()
alat_inval_multiple_entries(paddr, size)
alat_inval_single_entry(rtype, rega)
alat_read_memory_on_hit(ldtype, rtype,
raddr)
alat_translate_address_on_hit(ldtype,
rtype, raddr)
alat_write(ldtype, rtype, raddr, paddr,
size)
align_to_size_boundary(vaddr, size)
branch_predict(wh, ih, ret, target, tag)
Volume 3: Pseudo-Code Functions
There are several fault functions. Each fault function accepts parameters specific to
the fault, e.g., exception code values, virtual addresses, etc. If the fault is deferred for
speculative load exceptions the fault function will return with a deferral indication.
Otherwise, fault routines do not return and terminate the instruction sequence.
There are several trap functions. Each trap function accepts parameters specific to
the trap, e.g., trap code values, virtual addresses, etc. Trap routines do not return.
Ensures prior data memory references to uncached ordered-sequential memory
pages are "accepted" before subsequent data memory references are performed by
the processor.
Returns a one if the implementation finds an ALAT entry which matches the register
type specified by rtype and the register address specified by raddr , else returns
zero. This function is implementation specific. Note that an implementation may
optionally choose to return zero (indicating no match) even if a matching entry exists
in the ALAT. This provides implementation flexibility in designing fast ALAT lookup
circuits.
Notifies the ALAT of a change in the bottom of frame and/or size of frame. This allows
management of the ALAT's tag bits or other management functions it might need.
Invalidate all entries in the ALAT.
The ALAT is queried using the physical memory address specified by paddr and the
access size specified by size . All matching ALAT entries are invalidated. No value is
returned.
The ALAT is queried using the register type specified by rtype and the register
address specified by rega . At most one matching ALAT entry is invalidated. No value
is returned.
Returns a one if the implementation requires that the requested check load should
perform a memory access (requires prior address translation); returns a zero
otherwise.
Returns a one if the implementation requires that the requested check load should
translate the source address and take associated faults; returns a zero otherwise.
Allocates a new ALAT entry or updates an existing entry using the load type specified
by ldtype , the register type specified by rtype , the register address specified by
raddr , the physical memory address specified by paddr , and the access size
specified by size . No value is returned. This function guarantees that at most only
one ALAT entry exists for a given raddr . Based on the load type ldtype , if a
ld.c.nc , ldf.c.nc , or ldfp.c.nc instruction's raddr matches an existing ALAT
entry's register tag, but the instruction's size and/or paddr are different than that of
the existing entry's, then this function may either preserve the existing entry, or
invalidate it and write a new entry with the instruction's specified size and paddr .
Returns vaddr aligned to the boundary specified by size .
Implementation-dependent routine which updates the processor's branch prediction
structures.
Operation
3
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