Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1773

The MOVSS (Move scalar single-precision floating-point) instruction transfers a single
32-bit floating-point number from memory to a SSE register or vice versa, and between
registers.
4.6.1.7 State Management Instructions
The LDMXCSR (Load SSE Control and Status Register) instruction loads the SSE control
and status register from memory. STMXCSR (Store SSE Control and Status Register)
instruction stores the SSE control and status word to memory.
The FXSAVE instruction saves FP and MMX technology state and SSE state to memory.
Unlike FSAVE, FXSAVE does not clear the x87-FP state. FXRSTOR loads FP and MMX
technology state and SSE state from memory.
4.6.1.8 Additional SIMD Integer Instructions
Similar to the conversions instructions discussed in
Instructions" on page
original MMX technology instructions, in the presence of x87-FP instructions.
The PAVGB/PAVGW (Average unsigned source sub-operands, without incurring a loss in
precision) instructions add the unsigned data elements of the source operand to the
unsigned data elements of the destination register. The results of the add are then each
independently right shifted right by one bit position. The high order bits of each
element are filled with the carry bits of the sums. To prevent cumulative round-off
errors, an averaging is performed. The low order bit of each final shifted result is set to
1 if at least one of the two least significant bits of the intermediate unshifted shifted
sum is 1.
The PEXTRW (Extract 16-bit word from MMX technology register) instruction moves the
word in a MMX technology register selected by the two least significant bits of the
immediate operand to the lower half of a 32-bit integer register; the upper word in the
integer register is cleared.
The PINSRW (Insert 16-bit word into MMX technology register) instruction moves the
lower word in a 32-bit integer register or 16-bit word from memory into one of the four
word locations in a MMX technology register, selected by the two least significant bits of
the immediate operand.
The PMAXUB/PMAXSW (Maximum of packed unsigned integer bytes or signed integer
words) instruction returns the maximum of each pair of packed elements into the
destination register.
The PMINUB/PMINSW (Minimum of packed unsigned integer bytes or signed integer
words) instructions returns the minimum of each pair of packed data elements into the
destination register.
The PMOVMSKB (Move Byte Mask from MMX technology register) instruction returns an
8-bit mask formed of the most significant bits of each byte of its source operand in a
MMX technology register to an IA integer register.
Volume 4: IA-32 SSE Instruction Reference
4:469, these SIMD Integer instructions also behave identically to
Section 4.6.1.5, "Conversion
4:471