Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1083

mov pr
mov — Move Predicates
( ) mov
Format: qp r
( ) mov pr =
qp
( ) mov pr.rot =
qp
The source operand is copied to the destination register.
Description:
For moving the predicates to a GR, PR i is copied to bit position i within GR
For moving to the predicates, the source can either be a general register, or an
immediate value. In the to_form, the source operand is GR
specified by the immediate value
instruction in an
always one. The
therefore, is the mask bit for all of the rotating predicates. If there is a deferred
exception for GR
In the to_rotate_form, only the 48 rotating predicates can be written. The source
operand is taken from the
field, such that: imm
predicates. The immediate is sign extended to set the top 21 predicates. Bit position i in
the source operand is copied to PR i.
This instruction operates as if the predicate rotation base in the Current Frame Marker
(CFM.rrb.pr) were zero.
Operation:
if (PR[qp]) {
if (from_form) {
check_target_register(r
GR[r
for (i = 1; i <= 63; i++) {
}
GR[r
} else if (to_form) {
if (GR[r
tmp_src = sign_ext(mask
for (i = 1; i <= 63; i++) {
}
} else {
tmp_src = sign_ext(imm
for (i = 16; i <= 63; i++) {
}
}
}
Illegal Operation fault
Interruptions:
3:184
= pr
1
,
r mask
17
2
imm
44
field such that:
imm
16
value is sign extended. The most significant bit of
mask
17
(the NaT bit is 1), a Register NaT Consumption fault is taken.
r
2
operand (which is encoded in the instruction in an
imm
44
>> 16). The low 16-bits correspond to the static
= imm
28 44
] = 1;
1
GR[r ]{i} = PR[pr_phys_to_virt(i)];
1
].nat = 0;
1
].nat)
2
register_nat_consumption_fault(0);
if (tmp_src{i})
PR[pr_phys_to_virt(i)] = GR[r
// to_rotate_form
44
PR[pr_phys_to_virt(i)] = tmp_src{i};
are written. The value
mask
17
= >> 1. Predicate register 0 is
imm mask
17
16
);
1
// PR[0] is always 1
, 17);
17
]{i};
2
, 44);
Register NaT Consumption fault
from_form
to_form
to_rotate_form
.
r
1
and only those predicates
r
2
is encoded in the
mask
17
,
mask
17
imm
Volume 3: Instruction Reference
I25
I23
I24
28