INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manuals

Manuals and User Guides for INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3. We have 3 INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 manuals available for free PDF download: Manual

INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manual (1898 pages)

Brand: INTEL | Category: Software | Size: 11.16 MB

Table of Contents
4
1 About this Manual

14
2 Introduction to the Intel Itanium Architecture

24
- Introduction to the Intel ® Itanium ® Architecture
  24
- Operating Environments
  24
- Instruction Set Transition Model
  25
- System Environment
  25
  - Major Operating Environments
    25
  - Instruction Set Features
    26
- Instruction Level Parallelism
  26
- Compiler to Processor Communication
  27
- Control Speculation
  27
- Speculation
  27
  - Data Speculation
    28
  - Predication
    28
- Register Stack
  29
- Branching
  30
- Floating-Point Architecture
  30
- Register Rotation
  30
- Multimedia Support
  31
- Terminology
  32
- Application Register State
  34
3 Execution Environment

34
- Reserved and Ignored Registers and Fields
  34
6 IA-32 Application Execution Model in an Intel Itanium

120
- IA-32 Execution Layer
  120
- Hardware-Based IA-32 Application Execution
  120
- Instruction Set Modes
  121
- Instruction Set Transition Model
  121
- Instruction Set Mode Transitions
  124
- Application Registers
  124
- IA-32 Application Register Model
  125
- IA-32 Application Register Mapping
  126
- IA-32 General Registers (GR8 to GR15)
  128
- IA-32 Segment Register Selector Format
  129
- IA-32 Code/Data Segment Register Descriptor Format
  129
- IA-32 Segment Register Fields
  129
- IA-32 Environment Initial Register State
  131
- IA-32 Environment Runtime Integrity Checks
  133
- EFLAG Register (AR24)
  134
- IA-32 EFLAGS Register Fields
  135
- IA-32 Floating-Point Register Mappings
  136
- IA-32 Floating-Point Control Register (FCR)
  138
- Floating-Point Data Register (FDR)
  140
- Floating-Point Instruction Register (FIR)
  140
- SSE Registers (XMM0-XMM7)
  141
- Memory Addressing Model
  142
- Part II: Optimization Guide for the Intel
  146
  - Overview of the Optimization Guide
    148
  - Introduction to Programming for the Intel ® Itanium ® Architecture
    150
- Overview
  150
- Registers
  150
- Using Intel ® Itanium ® Instructions
  151
- Format
  151
- Expressing Parallelism
  151
- Bundles and Templates
  152
- Memory Access and Speculation
  153
- Functionality
  153
- Control Speculation
  153
- Predication
  154
- Data Speculation
  154
- Architectural Support for Procedure Calls
  155
- Stacked Registers
  155
- Register Stack Engine
  155
- Branches and Hints
  155
- Branch Instructions
  156
- Loops and Software Pipelining
  156
- Rotating Registers
  156
- Summary
  157
3 Memory Reference

158
2 Introduction to Programming for the Intel Itanium

158
- Overview
  158
- Non-Speculative Memory References
  158
- Stores to Memory
  158
- Loads from Memory
  158
- Data Prefetch Hint
  159
- Instruction Dependencies
  159
- Control Dependencies
  159
- Data Dependencies
  160
- Control Dependency Preventing Code Motion
  160
- Itanium ® Architecture
  161
- Using Data Speculation in the Intel Architecture
  163
- Combining Data and Control Speculation
  167
- Minimizing Code Size During Speculation
  170
- Using a Single Check for Three Advanced Loads
  172
- Flow Graph Illustrating Opportunities for Off-Path Predication
  178
- Software Pipelining and Loop Support
  192
- Ctop and Cexit Execution Flow
  198
- Ctop Loop Trace
  199
- Wtop and Wexit Execution Flow
  200
- Wtop Loop Trace
  202
- Floating-Point Applications
  216
- Software Divide/Square Root Sequence
  222
- Computational Models
  223
- Multiple Status Fields
  224
- Other Features
  225
- Memory Access Control
  227
- Summary
  228
- Itanium Architecture
  231
- Part I: Application Architecture Guide
  233
- Part 2: Optimization Guide for the Intel® Itanium® Architecture
  233
- Index
  239
- System Environment
  261
- Relationship between Instruction Type and Execution Unit Type
  897
- Template Field Encoding and Instruction Slot Mapping
  897
- Intel ® Itanium ® Architecture Software Developer's Manual Rev
  1191

INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manual (604 pages)

Brand: INTEL | Category: Software | Size: 2.64 MB

Table of Contents
4
1 About this Manual

8
2 Base IA-32 Instruction Reference

18
- Additional Intel ® Itanium ® Faults
  18
- Register Encodings Associated with the +Rb, +Rw, and +Rd Nomenclature
  20
  - Operation
    22
  - Flags Affected
    25
  - FPU Flags Affected
    25
- Bit Offset for BIT[EAX,21]
  25
- Memory Bit Indexing
  25
- Exception Mnemonics, Names, and Vector Numbers
  26
  - Floating-Point Exceptions
    27
  - Base Instruction Reference
    27
- Floating-Point Exception Mnemonics and Names
  27
- Information Returned by CPUID Instruction
  85
- Version Information in Registers EAX
  86
- Feature Flags Returned in EDX Register
  87
- FPATAN Zeros and Nans
  156
- FPREM Zeros and Nans
  158
- FPREM1 Zeros and Nans
  161
- FSUB Zeros and Nans
  190
- FSUBR Zeros and Nans
  193
- FYL2X Zeros and Nans
  206
- FYL2XP1 Zeros and Nans
  208
- IDIV Operands
  211
- INT Cases
  225
- LAR Descriptor Validity
  260
- LEA Address and Operand Sizes
  265
- Repeat Conditions
  345
  - Intel ® MMX™ Technology Instruction Reference
    406
- Operation of the MOVD Instruction
  408
- Operation of the MOVQ Instruction
  410
- Operation of the PACKSSDW Instruction
  412
- Operation of the PACKUSWB Instruction
  415
- Operation of the PADDW Instruction
  417
- Operation of the PADDSW Instruction
  420
- Operation of the PADDUSB Instruction
  423
- Operation of the PAND Instruction
  426
- Operation of the PANDN Instruction
  428
- Operation of the PCMPEQW Instruction
  430
- Operation of the PCMPGTW Instruction
  433
- Operation of the PMADDWD Instruction
  436
- Operation of the PMULHW Instruction
  438
- Operation of the PMULLW Instruction
  440
- Operation of the por Instruction
  442
- Operation of the PSLLW Instruction
  444
- Operation of the PSRAW Instruction
  447
- Operation of the PSRLW Instruction
  450
- Operation of the PSUBW Instruction
  453
- Operation of the PSUBSW Instruction
  456
- Operation of the PSUBUSB Instruction
  459
- High-Order Unpacking and Interleaving of Bytes with the PUNPCKHBW Instruction
  462
- Low-Order Unpacking and Interleaving of Bytes with the PUNPCKLBW Instruction
  465
- Operation of the PXOR Instruction
  468
3 IA-32 Intelmmx™ Technology Instruction Reference

470
- About the Intel ® SSE Architecture
  470
- IA-32 SSE Instructions
  470
4 IA-32 SSE Instruction Reference

470
- Single Instruction Multiple Data
  471
- New Data Types
  471
- Packed Single-FP Data Type
  471
  - Extended Instruction Set
    472
- SSE Register Set
  472
- Scalar Operation
  472
  - Instruction Group Review
    473
- Packed Operation
  473
- Packed Shuffle Operation
  475
- Unpack High Operation
  476
- Unpack Low Operation
  476
  - IEEE Compliance
    481
    
    Real Number System
    481
- Binary Real Number System
  482
- Binary Floating-Point Format
  483
- Real Number Notation
  483
- Real Numbers and Nans
  485
- Denormalization Process
  485
  - Operating on Nans
    487
  - Data Formats
    488
    
    Memory Data Formats
    488
    
    SSE Register Data Formats
    488
- Four Packed FP Data in Memory (at Address 1000H)
  488
- Results of Operations with NAN Operands
  488
- Precision and Range of SSE Datatype
  489
- Real Number and Nan Encodings
  489
  - Instruction Formats
    490
  - Instruction Prefixes
    490
- SSE Instruction Behavior with Prefixes
  490
- SIMD Integer Instructions - Behavior with Prefixes
  490
- Cacheability Control Instruction Behavior with Prefixes
  490
  - Reserved Behavior and Software Compatibility
    491
  - Notations
    491
- Key to SSE Naming Convention
  492
  - SIMD Integer Instruction Set Extensions
    569
  - Cacheability Control Instructions
    582
Index

590

INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manual (420 pages)

Architecture Software Developer's manual revision 2.3

Brand: INTEL | Category: Software | Size: 3.01 MB

Table of Contents

4
- 1 About this Manual
  
  10
- 2 Instruction Reference
  
  20
  - Instruction Page Font Conventions
    20
  - Register File Notation
    21
    
    Instruction Descriptions
    22
  - Pervasive Conditions Not Included in Instruction Description Code
    22
  - Add Pointer
    24
  - Stack Frame
    25
  - Branch Types
    29
  - Operation of Br.ctop and Br.cexit
    32
  - Operation of Br.wtop and Br.wexit
    33
  - Branch Cache Deallocation Hint
    33
  - Branch Whether Hint
    34
  - Sequential Prefetch Hint
    34
  - Long Branch Types
    39
  - IP-Relative Branch Predict Whether Hint
    41
  - Indirect Branch Predict Whether Hint
    41
  - Importance Hint
    41
  - ALAT Clear Completer
    44
Table of Contents

45
- ].Nat
  
  47
- Natval
  
  66
  - Specified Pc Mnemonic Values
    65
- If (Fail)
  
  70
  - If (Psr.tb)
    72
    
    Taken_Branch_Trap()
    72
  - IP = IP + Sign_Ext
    72
    
    (!Psr.it && Unimplemented_Physical_Address(IP)))
    72
    
    ((Psr.it && Unimplemented_Virtual_Address(IP, Psr.VM))
    72
    
    If (!Impl_Uia_Fault_Supported() && 21 << 4), 25)
    72
    
    Unimplemented_Instruction_Address_Trap(0, IP)
    72
  - Speculation_Fault
    72
  - Taken_Branch = 1
    72
  - Floating-Point Class Relations
    73
  - Floating-Point Classes
    73
  - Floating-Point Comparison Relations
    76
  - Floating-Point Comparison Types
    76
  - Fetch and Add Semaphore Types
    83
  - Floating-Point Merge Negative Sign Operation
    89
  - Floating-Point Merge Sign and Exponent Operation
    89
  - Floating-Point Merge Sign Operation
    89
  - Floating-Point MIX Left
    92
  - Floating-Point MIX Left-Right
    92
  - Floating-Point MIX Right
    92
  - Floating-Point Pack
    105
  - Floating-Point Parallel Comparison Relations
    110
  - Floating-Point Parallel Comparison Results
    110
  - Floating-Point Parallel Merge Negative Sign Operation
    120
  - Floating-Point Parallel Merge Sign Operation
    120
  - Floating-Point Parallel Merge Sign and Exponent Operation
    121
  - Floating-Point Swap
    146
  - Floating-Point Swap Negate Left
    146
  - Floating-Point Swap Negate Right
    147
  - Floating-Point Sign Extend Left
    148
  - Floating-Point Sign Extend Right
    148
  - Function of Getf.exp
    152
  - Function of Getf.sig
    152
  - Hint Immediates
    154
  - Load Types
    160
  - Sz Completers
    160
  - Load Hints
    161
  - FP Load Types
    166
  - Fsz Completers
    166
  - Lftype Mnemonic Values
    173
  - Lfhint Mnemonic Values
    174
  - MIX Examples
    179
  - Move to BR Whether Hints
    183
  - Indirect Register File Mnemonics
    189
  - Mux Permutations for 8-Bit Elements
    199
  - Mux2 Examples (16-Bit Elements)
    200
  - Pack Operation
    204
  - Pack Saturation Limits
    204
  - Parallel Add Examples
    206
  - Parallel Add Saturation Completers
    206
  - Parallel Add Saturation Limits
    206
  - Parallel Average Example
    210
  - Parallel Average with Round Away from Zero Example
    211
  - Parallel Average Subtract Example
    213
  - Parallel Compare Examples
    215
  - Pcmp Relations
    215
  - Parallel Multiply Operation
    222
  - Parallel Multiply and Shift Right Operation
    223
  - Parallel Multiply and Shift Right Shift Options
    223
  - Faults for Regular_Form and Fault_Form Probe Instructions
    227
  - Parallel Sum of Absolute Difference Example
    229
  - Parallel Shift Left Examples
    231
  - Parallel Subtract Examples
    236
  - Parallel Subtract Saturation Completers
    236
  - Parallel Subtract Saturation Limits
    236
  - Function of Setf.exp
    251
  - Function of Setf.sig
    251
  - Shift Left and Add Pointer
    255
  - Store Types
    260
  - Store Hints
    261
  - Xsz Mnemonic Values
    267
  - Test Bit Relations for Normal and Unc Tbits
    270
  - Test Bit Relations for Parallel Tbits
    270
  - Test Feature Features Assignment
    272
  - Test Feature Relations for Normal and Unc
    272
  - Test Feature Relations for Parallel
    272
  - Test Nat Relations for Normal and Unc Tnats
    275
  - Test Nat Relations for Parallel Tnats
    275
  - Memory Exchange Size
    283
- 3 Pseudo-Code Functions
  
  290
- 4 Instruction Formats
  
  302
- 5 Resource and Dependency Semantics
  
  380
  - Reading and Writing Resources
    380
  - Dependencies and Serialization
    380
  - Resource and Dependency Table Format Notes
    381
  - Semantics of Dependency Codes
    382
    
    RAW Dependency Table
    383
    
    Special Case Instruction Rules
    383
  - RAW Dependencies Organized by Resource
    384
    
    WAW Dependency Table
    392
  - WAW Dependencies Organized by Resource
    392
    
    WAR Dependency Table
    396
  - WAR Dependencies Organized by Resource
    396
  - Instruction Classes
    398

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INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manuals

INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manual (1898 pages)

Table of Contents

1 About this Manual

2 Introduction to the Intel Itanium Architecture

3 Execution Environment

6 IA-32 Application Execution Model in an Intel Itanium

3 Memory Reference

2 Introduction to Programming for the Intel Itanium

INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manual (604 pages)

Table of Contents

1 About this Manual

2 Base IA-32 Instruction Reference

3 IA-32 Intelmmx™ Technology Instruction Reference

4 IA-32 SSE Instruction Reference

Index

INTEL ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3 Manual (420 pages)

Table of Contents

Table of Contents

1 About this Manual

2 Instruction Reference

Table of Contents

].Nat

Natval

If (Fail)

3 Pseudo-Code Functions

4 Instruction Formats

5 Resource and Dependency Semantics

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