Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 964
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Operation:
if (PR[qp]) {
if (p
illegal_operation_fault();
if (tmp_isrcode = fp_reg_disabled(f
disabled_fp_register_fault(tmp_isrcode, 0);
tmp_rel = ((fclass
tmp_nat = fp_is_natval(FR[f
if (tmp_nat) {
PR[p
PR[p
} else {
PR[p
PR[p
}
} else {
if (fctype == 'unc') {
if (p
PR[p
PR[p
}
}
None
FP Exceptions:
Illegal Operation fault
Interruptions:
Volume 3: Instruction Reference
== p
)
1
2
{0} && !FR[f
9
&& ((fclass
9
(fclass
9
(fclass
9
(fclass
9
)
)
|| (fclass
{6} && fp_is_snan(FR[f
9
|| (fclass
{7} && fp_is_qnan(FR[f
9
|| (fclass
{8} && fp_is_natval(FR[f
9
] = 0;
1
] = 0;
2
] = tmp_rel;
1
] = !tmp_rel;
2
== p
)
1
2
illegal_operation_fault();
] = 0;
1
] = 0;
2
, 0, 0, 0))
2
].sign || fclass
2
{2} && fp_is_zero(FR[f
{3} && fp_is_unorm(FR[f
{4} && fp_is_normal(FR[f
{5} && fp_is_inf(FR[f
]))
2
]))
2
]));
2
]) && (!fclass
{8});
2
9
Disabled Floating-point Register fault
{1} && FR[f
].sign)
9
2
]))||
2
])) ||
2
])) ||
2
]))
2
fclass
3:65
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