Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1113

pmpyshr
pmpyshr — Parallel Multiply and Shift Right
( ) pmpyshr2
Format: qp
( ) pmpyshr2.u
qp
The four 16-bit data elements of GR
Description:
data elements of GR
(pmpyshr2), or unsigned (pmpyshr2.u). Each product is then shifted to the right
bits, and the least-significant 16-bits of each shifted product form 4 16-bit results,
which are placed in GR
gives the 16 high bits of the results. The allowed values for
Table 2-46.
Table 2-46.
count
Figure 2-37.
3:214
= , ,
r r r count
1 2 3 2
= , ,
r r r count
1 2 3 2
as shown in
r
3
. A of 0 gives the 16 low bits of the results, a
r count
1 2
Parallel Multiply and Shift Right Shift Options
2
0
7
15
16
Parallel Multiply and Shift Right Operation
GR r :
3
GR r :
2
*
Shift Right
count Bits
2
GR r :
1
are multiplied by the corresponding four 16-bit
r
2
Figure 2-37. This multiplication can either be signed
Selected Bit Field from Each 32-bit Product
15:0
22:7
30:15
31:16
* * *
pmpyshr2
signed_form
unsigned_form
count
of 16
count
2
are given in
count
2
16-bit
Source
Elements
32-bit
Products
16-bit
Result
Elements
Volume 3: Instruction Reference
I1
I1
2