Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1353

CALL—Call Procedure (Continued)
FI;
IF Itanium System Environment AND PSR.tb THEN IA_32_Exception(Debug);
FI;
IF far call AND (PE = 1 AND VM = 0) (* Protected mode, not virtual 8086 mode *)
THEN
IF segment selector in target operand null THEN #GP(0); FI;
IF segment selector index not within descriptor table limits
FI;
Read type and access rights of selected segment descriptor;
IF segment type is not a conforming or nonconforming code segment, call gate,
Depending on type and access rights
FI;
CONFORMING-CODE-SEGMENT:
IF DPL > CPL THEN #GP(new code segment selector); FI;
IF not present THEN #NP(selector); FI;
IF OperandSize = 32
THEN
ELSE (* OperandSize = 16 *)
FI;
IF Itanium System Environment AND PSR.tb THEN IA_32_Exception(Debug);
END;
NONCONFORMING-CODE-SEGMENT:
IF (RPL > CPL) OR (DPL  CPL) THEN #GP(new code segment selector); FI;
Volume 4: Base IA-32 Instruction Reference
Push(IP);
CS  DEST[31:16]; (* DEST is ptr16:16 or [m16:16] *)
EIP  DEST[15:0]; (* DEST is ptr16:16 or [m16:16] *)
EIP  EIP AND 0000FFFFH; (* clear upper 16 bits *)
THEN #GP(new code selector);
task gate, or TSS THEN #GP(segment selector); FI;
GO TO CONFORMING-CODE-SEGMENT;
GO TO NONCONFORMING-CODE-SEGMENT;
GO TO CALL-GATE;
GO TO TASK-GATE;
GO TO TASK-STATE-SEGMENT;
IF stack not large enough for a 6-byte return address THEN #SS(0); FI;
IF the instruction pointer is not within code segment limit THEN #GP(0); FI;
Push(CS); (* padded with 16 high-order bits *)
Push(EIP);
CS  DEST(NewCodeSegmentSelector);
(* segment descriptor information also loaded *)
CS(RPL)  CPL
EIP  DEST(offset);
IF stack not large enough for a 4-byte return address THEN #SS(0); FI;
IF the instruction pointer is not within code segment limit THEN #GP(0); FI;
Push(CS);
Push(IP);
CS  DEST(NewCodeSegmentSelector);
(* segment descriptor information also loaded *)
CS(RPL)  CPL
EIP  DEST(offset) AND 0000FFFFH; (* clear upper 16 bits *)
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